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rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106 u . s . a . tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 a 12-bit, 65 msps if to base band diversity receiver preliminary technical data AD6652 features integrated dual channel adc sample rates up to 65 msps if sampling frequencies to 200 mhz snr=70 db (to nyquist), sfdr 90 db (to nyquist) power-down to <2mw internal voltage reference internal sample & hold analog input flexible analog input (1 to 2 v p-p) differential or single-ended analog input clock duty cycle stabilizer -70 db channel-to-channel crosstalk quad-channel receive signal processor (rsp) crossbar switched receive processor inputs digital re-sampling for non-integer decimation rates programmable decimating fir filters flexible control for multi-carrier and phased array individual channel power-down functions to <1mw user configurable built in self test (bist) capability jtag boundary scan +3.0v analog, +3.3v i/o, +2.5 v cmos digital core applications communications diversity radios systems multi-mode digital receivers: gsm, phs, amps, umts, wcdma, cdma-one, is95, is136, cdma2000, edge, imt-2000 smart antenna systems general purpose software radios broadband data applications instrumentation and test equipment v i n b + v r e f s e n s e r e - r a m c o e f . f i l t e r n c o e x t e r n a l s y n c . c i r c u i t i n p u t m a t r i x n c o n c o n c o r a m c o e f . f i l t e r r a m c o e f . f i l t e r r a m c o e f . f i l t e r 1 2 1 2 s y n c a s y n c c s y n c b s y n c d c h a n n e l a c h a n n e l b c h a i n t e r p o l a t i n g h a l f b a n d f i l t e r & a g c c h b i n t e r p o l a t i n g a g c h a l f b a n d f i l t e r & r e - s a m p l e r c i c 5 r c i c 2 r e - s a m p l e r c i c 5 r c i c 2 r e - s a m p l e r c i c 5 r c i c 2 r e - s a m p l e r c i c 5 r c i c 2 o u t p u t m u x c i r c u i t r y c h a n n e l 0 c h a n n e l 1 c h a n n e l 2 c h a n n e l 3 p o r t b 8 - b i t d s p l i n k o r 1 6 - b i t p a r a l l e l o u t p u t c o n t r o l r c f o u t p u t s c h a . 0 , 1 , 2 , 3 , p o r t a 8 - b i t d s p l i n k o r 1 6 - b i t p a r a l l e l o u t p u t c o n t r o l v i n b - v r e f c l o c k d u t y c y c l e s t a b l i z e r b u f f e r b u f f e r a d c 1 2 1 2 r e f t a r e f b a r e f t b r e f b o e n a o e n b o t r a o t r b c h a n n e l b a c l k v i n a + v i n a - a d c s h a c h a n n e l a m o d e s e l e c t p d w n a s h r d r e f p d w n b d u t y e n r c f o u t p u t s c h a . 0 , 1 , 2 , 3 , . . . . . t o o u t p u t p o r t s t o o u t p u t p o r t s t o o u t p u t p o r t s t o o u t p u t p o r t s . . p r o g r a m s e r i a l i n p u t p o r t p s e u d o - r a n d o m n o i s e s e q u e n c e s d i s c l k 3 d a t a c o n t a d d 8 3 5 b u i l t - i n s e l f t e s t c i r c u i t r y p r o g r a m m i c r o p o r t j t a g r s p c l k d c l k i e e e 1 1 4 9 . 1 s h a 4 - c h a n n e l r e c e i v e s i g n a l p r o c e s s o r d u a l - c h a n n e l 1 2 - b i t a / d f r o n t e n d + 3 . 0 a v d d a g n d d g n d + 3 . 3 v d d i o 2 . 5 v d d functional block diagram
preliminary technical data AD6652 rev. pra 9/16/2002 2 product description the AD6652 is a mixed-signal if to base band receiver consisting of dual 12-bit 65 msps adcs and a quad channel multi-mode digital receive signal processor (rsp). the AD6652 is designed to support communications applications where low cost, small size, and versatility are desired. the AD6652 is also suitable for other applications in imaging, medical ultrasound, instrumentation, and test equipment. the multi-stage differential pipelined architecture adcs feature high performance sample-and-hold amplifiers with an integrated voltage reference. adc data outputs are directly tied to the receiver input matrix. over-range bits are available to alert the user to adc clipping. the digital receiver has four reconfigurable channels and provides extraordinary processing flexibility. the receiver input matrix feeds the adc outputs to any or all of the four receive processing channels. each receive-channel has five cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (nco)), two fixed-coefficient decimating filters (cic), a programmable ram coefficient decimating fir filter (rcf) and an interpolating halfband filter/agc stage. following the cic filters, a channel or all channels may be configured to use any or all of the rcf filters. this permits the processing power of four 160-tap rcf fir filters to be combined or used individually. after fir filtering the four channels are routed to two 16-bit output ports, and to two half-band interpolation stages where up to four channels may be combined (interleaved), interpol- ated and agc (automatic gain control) applied. the outputs from the two agc stages are also routed to both output ports. each output port has a 16-bit parallel output and an 8-bit link port to permit seamless data interface with dsp devices (such as the tigersharc tm ). a multiplexer for each port selects one of six data sources to appear on the device outputs pins. the AD6652 is part of analog devices? softcell? multi- mode and multi-carrier transceiver chipset. the softcell? receiver digitizes a wide spectrum of if frequencies and then down-converts the desired signals to base band using individual channel ncos. AD6652 user-configurable digital filters remove any undesired base band components and the data are then passed on to an external dsp where demodula- tion and other signal processing is performed to complete the information retrieval task. each receive channel is independently configured and provides simultaneous reception of the carrier it is tuned to. this if sampling architecture greatly reduces component cost and complexity compared with analog techniques or less integrated digital methods. high dynamic range decimation filters offer a wide range of decimation rates. the ram-based architecture allows easy reconfiguration for multi-mode applications. the decimating filters remove unwanted signals and noise from the channel of interest. when the channel occupies less bandwidth than the input signal, this rejection of out-of-band noise is called ?processing gain?. by using large decimation factors, this ?processing gain? can improve the snr of the adc by 30 db or more. in addition, the programmable ram coefficient filter allows anti-aliasing, matched filtering, and static equalization functions to be combined in a single, cost- effective filter. flexible power-down options allow significant power savings when desired. the adc stage can be powered-down to dissipate approximately 2mw while any of the receive processing channels can be individually or collectively powered-down. total chip power-down results in less than 3mw power dissipation. product highlights 1. integrated dual 12-bit 65 msps adc. 2. four independent digital filtering channels. 3. AD6652 operates from a 3v analog supply, 2.5v digital core supply, and a 3.3v i/o supply 4. proprietary sha input maintains excellent performance for input frequencies up to 200mhz, and can be configured for single-ended or differential operation. 5. crossbar-switched receive processor input ports 6. fractional digital re-sampling permits non-integer relationships between the adc clock and the digital output data rate. 7. power-down to less than 3mw. 8. adc over-range output bits. 9. 32-bit ncos with selectable amplitude and phase dithering for better than -100dbc spurious performance. 10. cic filters with user programmable decimation and interpolation factors 11. 160-tap programmable ram coefficient filter. 12. dual 16-bit parallel output ports and dual 8-bit link ports. 13. 8-bit microport and 2-wire serial port for register programming, register read-back and coefficient memory programming.
preliminary technical data AD6652 rev. pra 9/16/2002 3 contents features ................................................................ 1 applications ......................................................... 1 product description.................................... 2 product highlights ..................................... 2 contents ............................................................ 3 recommended operating conditions......................................................... 6 adc dc specifications (avdd = 3.0, vdd = +2.5v, vddio = +3.3v, 65 msps, 2v p-p differential input, 1.0v internal reference, unless otherwise noted) ........................................................... 6 typ............................................................... 6 adc switching specifications (avdd = 3.0, vdd = +2.5v, vddio = +3.3v, 65 msps, 2v p-p differential input, 1.0v internal reference, unless otherwise noted) ...................................... 6 temp............................................................ 6 typ............................................................... 6 adc ac specifications (avdd = 3.0, vdd = +2.5v, vddio = +3.3v, 65 msps, 2vp-p differential input, 1.0v internal reference, unless otherwise noted) ........................................................... 7 typ............................................................... 7 electrical characteristics (avdd = 3.0, vdd = +2.5v, vddio = +3.3v, 65 msps, 2vp-p differential input, 1.0v internal reference, unless otherwise noted) .................................................... 8 general timing characteristics 1, 2 (avdd = 3.0, vdd = +2.5v, vddio = +3.3v, 65 msps,2vp-p differential input, 1.0v internal reference, unless otherwise noted) ........................................................... 9 microprocessor port timing characteristics 1, 2 avdd = 3.0, vdd = +2.5v, vddio = +3.3v, 65 msps, 2vp-p differential input, 1.0v internal reference, unless otherwise noted) ......................................................... 10 microprocessor port, mode inm (mode=0) ........................... 10 microprocessor port, mode mnm (mode=1)......................... 10 absolute maximum ratings .................. 11 explanation of test levels................... 11 figure 1: pin configuration....................... 12 adc outputs ....................................... 14 receiver inputs ................................ 14 table 1: pin name and functions............ 14 definitions of a/d specifications........ 17 crosstalk .................................................................. 18 timing diagrams .......................................... 19 AD6652 theory of operation .................. 26 introduction..................................... 26 adc architecture ....................................... 26 analog input ..................................... 26 differential input configurations 27 single-ended input configuration 27 adc voltage reference............... 28 internal reference connection 28 external reference operation 29 clock input considerations ................................ 29 adc power-down mode................. 30 adc wake-up time ............................ 30 receive signal processor (rsp) architecture ................................................ 30 data input matrix ...................................... 30 numerically controlled oscillator ............ 30 2 nd order rcic filter ........................ 30 5 th order cic filter .......................... 30 ram coefficient filter ................. 30 interpolating half-band filters and agc ................................ 31 memory mapping and address notation .............................................................. 32 receive input matrix ........................................ 32 table iii. crossbar-switched routing of the two 12-bit adc data streams (a & b) using the rsp input matrix ......... 33 rsp data latency...................................... 33 frequency translation ............................... 33 nco frequency hold-off register........... 33 phase offset............................................... 33 nco control register............................... 33 by-pass...................................................... 33
preliminary technical data AD6652 rev. pra 9/16/2002 4 phase dither............................................... 33 amplitude dither....................................... 34 clear phase accumulator on hop ............ 34 reserved .................................................... 34 input select ................................................ 34 sync pin select .......................................... 34 2 nd order rcic filter ............................................ 34 rcic2 scale factor .................................... 35 rcic2 output level ................................... 35 rcic2 rejection......................................... 35 example calculations................................ 35 decimation and interpolation registers .................................................... 36 rcic2 scale register ................................. 36 5 th order cic filter ...................................... 36 cic5 rejection .......................................... 37 ram coefficient filter ............................. 37 rcf decimation register.......................... 37 rcf decimation phase.............................. 37 rcf filter length...................................... 38 rcf output scale factor and control register......................................... 38 interpolating half band filters ....... 39 automatic gain control ........................ 40 the agc loop .......................................... 40 desired signal level mode ....................... 40 desired clipping level mode ................... 42 synchronization......................................... 43 user configurable built in self test (bist) ......................................................... 43 ram bist ................................................ 43 channel bist ...................................... 44 chip synchronization ............................... 44 start ........................................................... 44 start with no sync.................................... 44 start with soft sync.................................. 45 start with pin sync ................................... 45 hop ............................................................ 45 set freq no hop........................................ 45 hop with soft sync................................... 45 hop with pin sync.................................... 46 parallel output ports ..................................... 46 channel mode............................................ 47 agc mode................................................. 48 master/slave pclk modes ....................... 48 parallel port pin functionality................... 48 link port .............................................................. 49 link port data format............................... 49 link port timing....................................... 50 tigersharc configuration ..................... 50 AD6652 channel address registers (partial listing) ........................................................... 50 0x00-0x7f: coefficient memory(cmem) ...................................... 51 0x80: channel sleep register .................. 51 0x81: soft_sync register ...................... 51 0x82: pin_sync register ....................... 51 0x83: start hold-off counter .................. 51 0x84: nco frequency hold-off counter ...................................................... 51 0x85: nco frequency register 0 ............ 52 0x86: nco frequency register 1 ............ 52 0x87: nco phase offset register............ 52 0x88: nco control register.................... 52 0x90: rcic2 decimation ? 1 (m rcic2 -1)................................................... 53 0x91: rcic2 interpolation ? 1 (l rcic2 -1).................................................... 53 0x92: rcic2 scale .................................... 53 0x93:.......................................................... 54 0x94: cic5 decimation ? 1 (m cic5 - 1)................................................................ 54 0x95: cic5 scale ..................................... 54 0x96:.......................................................... 54 0xa0: rcf decimation ? 1 (m rcf - 1)................................................................ 54 0xa1: rcf decimation phase (p rcf )......................................................... 54 0xa2: rcf number of taps minus one (n rcf -1) .............................................. 54 0xa3: rcf coefficient offset (co rcf )...................................................... 54 0xa4: rcf control register.................... 54 0xa5: bist register for i ........................ 55 0xa6: bist register for q ...................... 55 0xa7: bist control register................... 55 0xa8: ram bist control register......... 55 0xa9: output control register ................ 55 0x00 through 0x07 .................................... 55 0x08 port a control register.................... 55 0x09 port b control register .................... 56 0x0a agc a control register ................. 56
preliminary technical data AD6652 rev. pra 9/16/2002 5 0x0b agc a hold off counter................. 56 0x0c agc a desired level....................... 56 0x0d agc a signal gain......................... 56 0x0e agc a loop gain ........................... 56 0x0f agc a pole location ...................... 57 0x10 agc a average samples................. 57 0x11 agc a update decimation.............. 57 0x12 agc b control register .................. 57 0x13 agc b hold off counter ................. 57 0x14 agc b desired level........................ 57 0x15 agc b signal gain .......................... 58 0x16 agc b loop gain............................ 58 0x17 agc b pole location....................... 58 0x18 agc b average samples ................. 58 0x19 agc b update decimation.............. 58 0x1a parallel port control a .................... 58 0x1b link port control a ......................... 58 memory map for output port control registers ................................................................ 60 0x1c parallel port control b..................... 62 0x1d link port control b ......................... 62 0x1e port clock control ........................... 62 microport control.................................... 62 external memory map............................... 63 access control register (acr) ................ 63 channel address register (car) ............. 64 soft_sync control register................. 64 pin_sync control register .................... 64 sleep control register............................ 64 data address registers ............................. 65 write sequencing ...................................... 65 read sequencing ....................................... 65 read/write chaining................................. 65 intel non-multiplexed mode (inm) ......... 65 motorola non-multiplexed mode (mnm) ...................................................... 65 serial port control.................................. 65 serial port timing specifications ............. 66 sdin.......................................................... 66 sclk......................................................... 66 jtag boundary scan.................................. 67 internal write access ............................. 67 write pseudocode...................................... 67 internal read access ............................... 68 read pseudocode....................................... 68 AD6652 evaluation board and software ............................................................. 68
preliminary technical data AD6652 rev. pra 9/16/2002 6 recommended operating conditions parameter temp test level min AD6652as typ max units avdd tbd 3.0 tbd v vdd iv 2.375 2.5 2.675 v vddio iv 3.0 3.3 3.6 v t ambient iv -40 +25 +70 ?
preliminary technical data AD6652 rev. pre 9/16/2002 7 adc ac specifications (avdd = 3.0, vdd = +2.5v, vddio = +3.3v, 65 msps, 2vp-p differential input, 1.0v internal reference, unless otherwise noted) parameter (conditions) temp test level min AD6652 typ max units tbd tbd tbd notes 1 2 specifications subject to change without notice
preliminary technical data AD6652 rev. pra 9/16/2002 8 electrical characteristics (avdd = 3.0, vdd = +2.5v, vddio = +3.3v, 65 msps, 2vp-p differential input, 1.0v internal reference, unless otherwise noted) parameter (conditions) temp test level min AD6652 typ max units logic inputs (5v tolerant) logic compatibility full iv 3.3v cmos logic ?1? voltage full iv 2.0 5.0 v logic ?0? voltage full iv -0.3 0.8 v logic ?1? current full iv 1 10 a logic ?0? current logic ?1? current (inputs with pull-down) logic ?0? current (inputs with pull-up) full full full iv iv iv 1 10 a input capacitance 25
preliminary technical data AD6652 rev. pra 9/16/2002 9 general timing characteristics 1, 2 (avdd = 3.0, vdd = +2.5v, vddio = +3.3v, 65 msps,2vp-p differential input, 1.0v internal reference, unless otherwise noted) parameter (conditions) temp test level min AD6652 typ max units dclk timing requirements: tdclk dclk period full i 12.5 ns tdclkl dclk width low full iv 5.6 0.5 x t clk ns tdclkh dclk width high full iv 5.6 0.5 x t clk ns /reset timing requirements: t resl /reset width low full i 30.0 ns input wideband data timing requirements: t si input to
preliminary technical data AD6652 rev. pra 9/16/2002 10 1 all timing specifications valid over vdd range of 2.25v to 2.75v and vddio range of 3.0v to 3.6v. 2 (c load =40pf on all outputs unless otherwise specified) 3 the timing parameters for px[15:0], pxreq, pxack, lxclkout, lx[7:0] apply for port a and b. (x stands for a or b) specifications subject to change without notice microprocessor port timing characteristics 1, 2 avdd = 3.0, vdd = +2.5v, vddio = +3.3v, 65 msps, 2vp-p differential input, 1.0v internal reference, unless otherwise noted) AD6652 microprocessor port, mode inm (mode=0) temp test level min typ max units mode inm write timing: t sc control 3 to
preliminary technical data AD6652 rev. pra 9/16/2002 11 absolute maximum ratings avdd?????.????.???.. ?0.3 to +3.9v vdd???.?.????????? ?0.3 to +2.75v vddio????????..???.?.?0.3 to +3.6v vina, vinb????????.-0.3 to avdd +0.3v digital input voltage?????.-0.3 to avdd +0.3v output voltage swing??.?..-0.3v to vddio +0.3v load capacitance????.???..?????.200pf operating temperature range????.-40
preliminary technical data AD6652 rev. pra 9/16/2002 12 figure 1: pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a dgnd pa7_ la7 a2 pa6_ la6 d1 d3 /cs /reset mode syncd otrb pdwn b avdd avdd agnd agnd b tdo pa4_ la4 pach0_ laclk out a0 /trst r/w (/wr) d4 d6 syncc synca /oenb dutyen avdd avdd agnd agnd c pa9 pa3_ la3 a1 /ds (rd) d0 d2 d5 d7 /dtack (rdy) syncb n.c. n.c. avdd avdd agnd vin+b d pa1_ la1 pa2_ la2 pach1_ laclk in vdd vdd vdd vdd vddio vddio vddio vddio vddio avdd avdd agnd vin-b e pa8 pa5_ la5 n.c. vdd vdd vdd vdd vddio vddio vddio vddio vddio avdd avdd agnd agnd f pa0_ la0 tclk pa10 dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd vddio avdd agnd agnd agnd g pa12 pa11 pa13 dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd vddio avdd agnd refb b reftb h pareq pa15 pa14 dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd vddio avdd agnd agnd sense j chip_ id1 tdi tms dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd vddio avdd agnd agnd vref k chip_ id3 paack chip_ id0 dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd vddio avdd agnd refb a refta l pb6_ lb6 pb7_ lb7 sclk dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd vddio avdd agnd agnd agnd m chip_ id2 pb3_ lb3 pb4_ lb4 vddio vddio vddio vddio vdd vdd vdd vdd vddio avdd avdd agnd agnd n paiq pbch1_ lbclk in pb2_ lb2 vddio vddio vddio vddio vdd vdd vdd vdd vddio avdd avdd agnd vin-a p sdin pb0_ lb0 pb8 pb10 pb14 reserved vddio pback n.c. n.c. n.c. otra n.c. avdd avdd agnd vin+a r pbiq pbch0_ lbclk out pb1_ lb1 pb9 pb12 pb15 n.c. n.c. n.c. n.c. /oena pdwn a avdd avdd agnd agnd t dgnd pclk pb5_ lb5 pb11 pb13 pbreq n.c. n.c. n.c. n.c. dclk shrd ref avdd aclk agnd agnd
preliminary technical data AD6652 rev. pra 9/16/2002 13 17 mm sq. 1.0 mm 256 lead bga (17mm x 17mm) top view kjhgfedcba 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tr ml pn kjhgfedcba tr ml pn ball legend vddio vdd avdd digital ground analog ground i/o no connect figure 2. 17 x 17 mini-bga package showing power and signal ball assignments
preliminary technical data AD6652 rev. pra 9/16/2002 14 table 1: pin name and functions name type function power supply avdd p 3.0v analog supply, 25 pins vdd p 2.5v digital core supply, 16 pins vddio p 3.3v digital i/o supply, 27 pins dgnd g digital ground, 50 pins agnd g analog ground, 28 pins n.c. --- no connect, 15 pins adc inputs vin+a i differential analog input pin (+) for channel a vin-a i differential analog input pin (-) for channel a vin+b i differential analog input pin (+) for channel b vin-b i differential analog input pin (-) for channel b vref i/o voltage reference input/output sense i voltage reference mode selection aclk i adc master clock dutyen i duty cycle stabilizer (dcs) mode pdwna 1 i power-down function (active high) pdwnb 1 i power-down function (active high) /oena i output enable for channel a (active low) /oenb i output enable for channel a (active low) shrdref i shared reference control bit (low = independent mode, high = shared mode adc outputs otra o out of range indicator for channel a otrb o out of range indicator for channel b refta o top reference voltage for channel a reftb o top reference voltage for channel b refba o bottom reference voltage for channel a refbb o bottom reference voltage for channel b receiver inputs /reset i active low reset pin dclk i receive signal processor master clock pclk i/o link/parallel port clock pach1_laclkin 2 i/o parallel port a channel identification msb output or link port a data ready. function depends on value of bit 7 at 0x1b, output port control register. pbch1_lbclkin 2 i/o parallel port b channel identification msb output or link port b data ready input. function depends on value of bit 7 at 0x1d. output port control register. synca 3 i hardware sync, connects to all four rsp channels syncb 3 i hardware sync, connects to all four rsp channels syncc 3 i hardware sync, connects to all four rsp channels syncd 3 i hardware sync, connects to all four rsp channels /cs 3 i chip select (low active) chip_id[3:0] 3 i chip id selector, 4 pins
preliminary technical data AD6652 rev. pra 9/16/2002 15 receiver outputs pach0_laclkout 2 o parallel port a channel identification lsb output or link port a clock output. function depends on value of bit 7 at 0x1b, output port register. pbch0_lbclkout 2 o parallel port b channel identification lsb output or link port b clock output. function depends on value of bit 7 at 0x1d, output port register. pa [7:0]_la[7:0] o link port a output data or parallel data port a lsbs (depends on value of bit 7 at 0x1b, output port register), eight pins pb [7:0]_lb[7:0] o link port b output data or parallel data port b lsbs (depends on value of bit 7 at 0x1d, output port register), eight pins pa[15:8] o parallel data port a, bits 15:8, eight pins pb[15:8] o parallel data port b, bits 15:8, eight pins paiq o parallel port a i/q data indicator pbiq o parallel port b i/q data indicator jtag & bist /trst 5 i test reset pin tclk 3 i test clock input tms 5 i test mode select input tdo o/t test data output tdi 5 i test data input 1 pdwna and pdwnb must be the same logic level, both logic high or both logic low 2 pach0 and pach1 form a 2-bit output word in the parallel output mode that identifies the processing channel (0,1,2 or 3) whose data appears on port a parallel outputs. likewise, pbch0 and pbch1 identify the channel for port b. 3 pins with a pull-down resistor of nominal 70k ohms 4 mode 0 = intel non-multiplexed (imn) and mode 1= motorola non-multiplexed (mnm) control paack i parallel port a acknowledge pareq o parallel port a request pback i parallel port b acknowledge pbreq o parallel port b request microport control d[7:0] i/o/t bi-directional microport data, eight pins a[2:0] i microport address bus, three pins /ds(/rd) 4 i active low data strobe (active low read) (pin function depends upon mode. ( ) =mode 0 /dtack(rdy) 4,5 o/t active low data acknowledge (microport status bit) (pin function depends upon mode. ( ) =mode 0 r/w (/wr) 4 i read write (active low write) (pin function depends upon mode. ( ) =mode 0 mode 4 i mode select, intel (logic 0) or motorola (logic 1) serial port control sdin 3 i serial port control data input sclk 3 i serial port control clock
preliminary technical data AD6652 rev. pra 9/16/2002 16 5 pins with a pull-up resistor of nominal 70k ohms
preliminary technical data AD6652 rev. pra 9/16/2002 17 definitions of a/d specifications integral nonlinearity (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an ideal a/d converter exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges. zero error the major carry transition, 011111111111 to 100000000000, should occur when analog input voltage is ? lsb below vin- = vin+. zero error is defined as the voltage deviation of the actual transition from the ideal transition. gain error the first code transition should occur at an analog value 1/2 lsb above negative full scale. the last transition should occur at an analog value 1 1/2 lsb below the positive full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. temperature drift the temperature drift for zero error and gain error specifies the maximum change from the initial (25 o c) value to the value at tmin or tmax. power supply rejection ratio (psrr) the specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. aperture jitter aperture jitter is the variation in aperture delay for successive samples and can be manifested as noise on the input to the a/d converter. aperture delay aperture delay is a measure of the sample-and-hold amplifier (sha) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. signal-to-noise and distortion (s/n+d, sinad) ratio s/n+d is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the number of bits. using the following formula, n = (sinad - 1.76)/6.02 it is possible to obtain a measure of performance expressed as n, the effective number of bits. thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. spurious free dynamic range (sfdr) sfdr is the difference in db between the rms amplitude of the input signal and the peak spurious signal. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. may be reported in dbc (i.e., degrades as signal levels are lowered) or in dbfs (always related back to converter full scale). clock pulse width and duty cycle pulse width high is the minimum amount of time that the clock pulse should be left in the logic 1 state to achieve rated performance: pulse width low is the minimum time the clock pulse should be left in the low state. at a given clock rate, these specifications define an acceptable clock duty cycle. minimum conversion rate the clock rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the clock rate at which parametric testing is performed.
preliminary technical data AD6652 rev. pra 9/16/2002 18 output propagation delay the delay between the clock logic threshold and the time when all bits are within valid logic levels. out-of-range recovery time out-of-range recovery time is the time it takes for the a/d converter to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. crosstalk coupling onto one channel being driver by a low level (- 40dbfs) signal when the adjacent interfering channel is driven by a full-scale signal. nyquist sampling (oversampling) occurs when the frequency components of the analog input signal are confined between dc and the sample rate/2. requires the analog input frequency to be sampled at least 2 samples per cycle. if sampling (undersampling) due to the effects of aliasing, an adc is not necessarily limited to nyquist sampling. frequencies above nyquist will be aliased and appear in the first nyquist zone (dc to sample rate/2). care must be taken to limit the bandwidth of the sampled signal so that it does not overlap nyquist zones and alias onto itself . if sampling performance is limited by the bandwidth of the input sha (sample and hold amplifier) and clock ?jitter?. the sample rate of the analog input frequency will be less than 2 samples per cycle.
preliminary technical data AD6652 rev. pra 9/16/2002 19 timing diagrams reset t resl figure 3. reset timing requirements sclk t sclkl t sclkh figure 4. sclk switching characteristics sdin sclk t ssi datan t hsi figure 5. serial port input timing characteristics synca syncb syncc syncd dclk t ss t hs figure 6. sync timing inputs
preliminary technical data AD6652 rev. pra 9/16/2002 20 pclk dclk t dpoclkl figure 7. pclk to dclk switching characteristics divide by 1 t poclkl t poclklh pclk dclk t dpoclkll figure 8. pclk to dclk switching characteristics divide by 2,4, or 8 pclk pxack t spa t hpa figure 9. master mode pxack to pclk setup and hold characteristics
preliminary technical data AD6652 rev. pra 9/16/2002 21 pclk pxreq pxack px[15:0] data 1 data 2 t dpp t spa data n-1 data n t spa t dpp figure 10. master mode pxack to pclk switching characteristics pxreq pxack px[15:0] pclk t dpreq data 1 data n t dpp t dpp figure 11. master mode pxreq to pclk switching characteristics pclk pxack t spa t hpa t poclkh t poclkl figure 12. slave mode pxack to pclk setup and hold characteristics
preliminary technical data AD6652 rev. pra 9/16/2002 22 pclk pxreq pxack px[15:0] data 1 data 2 t dpp t spa data n-1 data n t spa t dpp figure 13. slave mode pxack to pclk switching characteristics pxreq pxack px[15:0] pclk t dpreq data 1 data n t dpp t dpp figure 14. slave mode pxreq to pclk switching characteristics pclk lxclkout t fdlclk t rdlclk figure 15. lxclkout to pclk switching characteristics
preliminary technical data AD6652 rev. pra 9/16/2002 23 lxclkout lxclkin lx[7:0] d0 d1 d2 d3 wait >= 6 cycles one time connectiivity check d15 8 lxclkout cycles d0 d1 d2 d3 d4 next transfer begins next transfer acknowledge figure 16. lxclkin to lxclkout data switching characteristics lxclkout lx[7:0] t fdlclkdat t rdlclkdat figure 17. lxclkout to lx[7:0]data switching characteristics
preliminary technical data AD6652 rev. pra 9/16/2002 24 timing diagrams ? inm microport mode t sam /rd (/ds) /wr (rw) /cs a[2:0] d[7:0] rdy (/dtack) valid address valid data t sam t ham t ham t drdy t hwr t acc notes: 1. t acc access time depends on the address accessed. access time is measured from fe of /wr to re of rdy. t acc requires a maximum of 9 clk periods t sc t hc clk figure 18. inm microport write timing requirements. t sam /rd (/ds) /wr (rw) /cs a[2:0] d[7:0] rdy (/dtack) valid address t drdy t acc valid data t ha notes: 1. t acc access time depends on the address accessed. access time is measured from fe of /wr to re of rdy. t acc requires a maximum of 13 clk periods t sc t hc clk figure 19. inm microport read timing requirements.
preliminary technical data AD6652 rev. pra 9/16/2002 25 timing diagrams ? mnm microport mode t sam /ds (/rd) rw (/wr) /cs a[2:0] d[7:0] /dtack (rdy) valid address valid data t sam t ham t ham t hrw t acc t hds t ddtack notes: 1. t acc access time depends on the address accessed. access time is measured from the fe of /ds to the fe of /dtack. t acc requires a maximum of 9 clk periods t sc t hc clk figure 20. mnm microport write timing requirements. t sam /ds (/rd) rw (/wr) /cs a[2:0] d[7:0] /dtack (rdy) valid address t hds t acc valid data t ha t ddtack notes: 1. t acc access time depends on the address accessed. access time is measured from the fe of /ds to the fe of /dtack. t acc requires a maximum of 13 clk periods t sc t hc clk figure 21. mnm microport read timing requirements.
preliminary technical data AD6652 rev. pra 9/16/2002 26 AD6652 theory of operation introduction the AD6652 has two analog input channels, four digital filtering channels and two digital output channels. the signal at each output channel may experience up to seven signal-processing operations: 1. 12-bit a/d conversion 2. frequency translation (from if to baseband) 3. second order re-sampling cascaded integrator comb fir filtering (rcic2) 4. fifth order cascaded integrator comb fir filtering (cic5) 5. ram coefficient fir filtering (rcf) 6. automatic gain control (agc) 7. 2x interpolation the digitally filtered channels allow up to four signals to be concurrently processed from the adc stage. flexible channel multiplexing allows one to four channels to be interleaved onto one output port. four synchronization input pins allow AD6652 start-up and frequency hop functions to be precisely orchestrated with other devices. the ncos phase can be programmed to produce carriers with known phase offset. programming and control is accomplished using either 2-wire serial or 8-bit parallel microport interfaces. adc architecture the AD6652 front-end consists of two 12-bit a/d converters, preceded by high performance sample-and-hold amplifiers (sha) capable of excellent performance up to 200 mhz. a flexible, integrated voltage reference allows analog inputs up to 2v p-p. an over-range bit for each channel is provided to signal when an out-of-range condition exists. both adc channels are internally routed to the input matrix of the receive signal processor (rsp) stage for channel routing, frequency translation, baseband filtering and data output configuration. each sample and hold amplifier (sha) is followed by a pipelined switched capacitor a/d converter. the pipelined a/d converter is divided into three sections, consisting of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. each stage provides sufficient overlap to correct for flash errors in the preceding stages. the quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capacitor dac and inter-stage residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. analog input the analog inputs to the AD6652 are differential switched capacitor shas that have been designed for optimum performance while processing differential ac or dc input signals. the sha input can support a wide common-mode range and maintain excellent performance. an input common-mode voltage of mid-supply will minimize signal- dependant errors and provide optimum performance. + - s s s s h h vina+ vina- 5 pf 5 pf s = sample h = hold avdd . . . . . . . avdd . figure 22. switched-capacitor sha input for one adc channel referring to figure 22, the clock signal alternatively switches the sha between sample mode and hold mode. when the sha is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network will create a low-pass filter at the
preliminary technical data AD6652 rev. pra 9/16/2002 27 adc?s input; therefore, the precise values are dependant upon the application. in if under-sampling applications, any shunt capacitors should be removed. in combination with the driving source impedance, they would limit the input bandwidth. for best dynamic performance, the source impedances driving the differential analog inputs should be matched such that common-mode settling errors are symmetrical. these errors will be reduced by the common-mode rejection of the adc. the sha may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. the minimum and maximum common- mode input levels are defined as follows: vcm min = vref/2, vcm max = (avdd + vref)/2 the minimum common-mode input level allows the AD6652 to accommodate ground-referenced inputs. although optimum performance is achieved with a differential input, a single-ended source may be driven into vina or vinb. in this configuration, one input will accept the signal, while the opposite input should be set to mid- scale by connecting it to an appropriate reference. for example, a 2 v p-p signal may be applied to vina while a 1 v reference is applied to vinb. the AD6652 will then accept a signal varying between 2 v and 0 v. in the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. however, the effect will be less noticeable at lower input frequencies. differential input configurations as previously detailed, optimum performance will be achieved while driving the AD6652 inputs in a differential input configuration. for baseband (dc to 32.5 mhz) applications, the ad8138 differential driver provides excellent performance and a flexible interface to the a/d converter. the output common-mode voltage of the ad8138 is easily set to avdd/2, and the driver can be configured in a sallen key filter topology to provide band limiting of the input signal. the schematic diagram in figure 23 is a recommended example of a baseband differential driver for the AD6652 inputs. at input frequencies above the nyquist zone (>32.5 mhz), the performance of most amplifiers will not be adequate to achieve the true performance of the AD6652 adc stage. this is especially true in if under-sampling applications where frequencies in the 70 mhz to 200 mhz range are being sampled. for these applications, differential trans- former coupling is the recommended input configuration as shown in figure 24. a d 8 1 3 8 + - t o v i n a + t o v i n a - 1 v p - p 0 . 1 u f a v d d 1 k 1 k 4 9 . 9 4 9 9 4 9 9 4 9 9 5 2 3 5 0 5 0 1 0 p f 1 0 p f . . . . . . . . figure 23. differential input for a single channel of the AD6652 using the ad8138 for nyquist applications (dc to 32.5 mhz). 2 v p - p 4 9 . 9 0 . 1 u f t o v i n a + 1 0 p f t o v i n a - 1 0 p f 2 2 2 2 1 k 1 k a v d d . . . . . . . t 1 figure 24. differential transformer-coupled input for a single channel of the AD6652. the circuit in figure 24 should be considered for input frequencies above the first nyquist zone (32.5 to 200 mhz). t1 is a broadband center-tapped 1:1 rf transformer such as mini circuits t1-1t.the signal characteristics must be considered when selecting a transformer. some rf transformers will saturate at frequencies below a few mhz, and excessive signal power can also cause core saturation, which leads to distortion. single-ended input configuration a single-ended input may provide adequate performance in cost-sensitive applications. in this configuration there will be degradation in sfdr and distortion performance due to
preliminary technical data AD6652 rev. pra 9/16/2002 28 the large input common-mode swing. however, if the source impedances on each input are matched, there should be little effect on snr performance. figure 25 details a typical single-ended input configuration. 2v p-p 50 0.1uf to vina+ 10pf to vina- 10pf 22 22 1k 1k avdd .. 10uf 0.1uf . 1k 1k avdd . 10 uf + . .. . figure 25. ac-coupled single-ended input for a single adc input channel adc voltage reference an internal differential reference buffer creates positive (top) and negative (bottom) reference voltages, reft and refb, respectively, that define the span of the adc core. the output common mode of the reference buffer is set to mid-supply, and the reft and refb voltages and span are defined as follows: reft = 1/2 (avdd + vref), refb = 1/2 (avdd - vref), span = 2 x (reft-refb) = 2 x vref. it can be seen from the equations above that the reft and refb voltages are symmetrical about the mid-supply voltage and, by definition, the input span is twice the value of the vref voltage. the internal voltage reference can be pin-strapped to fixed values of 0.5 v or 1.0 v, or adjusted within the same range as discussed in the internal reference connection section. maximum snr performance will be achieved with the reference set to the largest input span of 2 vp-p. the relative snr degradation will be 3 db when changing from 2 vp-p mode to 1 vp-p mode. a stable and accurate 0.5 v voltage reference is built into the AD6652. the input range can be adjusted by varying the reference voltage applied to the AD6652, using either the internal reference or an externally applied reference voltage. the input span of each adc tracks reference voltage changes linearly. if the adc is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage). internal reference connection a comparator within the AD6652 detects the potential at the sense pin and configures the reference into four possible states, which are summarized in table ii. if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 27), setting vref to 1 v. connecting the sense pin to vref switches the reference amplifier output to the sense pin, completing the loop and providing a 0.5 v reference output. if a resistor divider is connected as shown in figure fff, the switch will again be set to the sense pin. this will put the reference amplifier in a non-inverting mode with the vref output defined as follows: vref = 0.5 x (1 + r2/r1)in all reference configurations, reft and refb drive the a/d conversion core and establish its input span. the input range of the adc always equals twice the voltage at the reference pin for either an internal or an external reference. table ii. reference sense operation sense voltage internal switch position selected mode resulting vref (v) resulting differential span (v p-p) avdd n/a external reference n/a 2 x external reference vref sense internal fixed reference 0.5 1.0 0.2 v to vref sense programmable reference 0.5 x (1+r2/r1) 2 x vref (see fig. yyy) agnd to 0.2v internal divider internal fixed reference 1.0 2.0
preliminary technical data AD6652 rev. pra 9/16/2002 29 + - ch a adc core + - 0.5 v . . .. . . . . . 0.1uf 0.1uf 10 uf 0.1uf . refb_a reft_a vref sense vin a - vin a + 0.1uf . . select logic . . 10 uf . . + - . to ch b ref amp ref amp a vref figure 26. fixed reference configuration showing the common vref and ch.a connections. ch. b connections are identical to those of ch. a. external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift characteristics. when multiple adcs track one another, a single reference (internal or external) may be necessary to reduce gain-matching errors to an acceptable level. a high precision external reference may also be selected to provide lower gain and offset temperature drift. when the sense pin is tied to avdd, the internal reference will be disabled, allowing the use of an external reference. an internal reference buffer will load the external reference with an equivalent 7 k ?
preliminary technical data AD6652 rev. pra 9/16/2002 30 the aclk clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD6652 adc stage. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the aclk clock is generated from another type of source (by gating, dividing, or other methods), it should be re-timed by the original clock at the last step. adc power-down mode the power dissipated by the AD6652 front end adc is proportional to its sampling rate. normal adc operation requires that pdwna and pdwnb be set to logic low. however, the adc can be placed in a power-down mode by setting the pdwna or pdwnb pins to logic high. in this mode, the adc sampling rate is irrelevant. low power dissipation in power-down mode is achieved by shutting-down the reference buffers and biasing networks of both channels. in this mode, power consumption of the adc drops from a maximum of 600mw during normal operation to <2mw. both power down pins must be either high or low for proper adc operation. adc wake-up time the decoupling capacitors on reft and refb are discharged when entering standby mode, and then must be recharged when returning to normal operation. as a result, the wake-up time is related to the time spent in standby mode, and shorter standby cycles will result in proportionally shorter wake-up times. with the recommended 0.1 f and 10 f decoupling capacitors on reft and refb, it takes approximately one second to fully discharge the reference buffer decoupling capacitors, and 5 ms to restore full operation. receive signal processor (rsp) architecture data input matrix the rspsection features dual high-speed 12-bit input ports that are capable of crossbar multiplexing of data to the four processing channels that follow the input matrix. in addition, a third input option to the matrix is available to facilitate bist (built-in self test). this option is a pn (pseudo-random noise) sequence. the dual input ports allow unusual flexibility with a single tuner chip. these can be diversity inputs or truly independent inputs such as separate antenna segments. either input port or the pn sequence can be routed to any or all of the four tuner channels. this flexibility allows for up to 4 different analog sources to be processed simultaneously. numerically controlled oscillator frequency translation is accomplished with a 32-bit complex numerically controlled oscillator (nco). each of the four processing channels contains a separate nco. real data entering this stage is separated into in-phase (i) and quadrature (q) components. this stage translates the input signal from a digital intermediate frequency (if) to digital baseband. phase and amplitude dither may be enabled on-chip to improve spurious performance of the nco. a phase-offset word is available to create a known phase relationship between multiple AD6652s or between channels. 2 nd order rcic filter following frequency translation is a re-sampling, fixed coefficient, high speed, second order, re-sampling cascade integrator comb (rcic2) filter that reduces the sample rate based on the ratio between the decimation and interpolation registers. the re-sampler allows for non- integer relationships between the master clock and the output data rate. this stage may be bypassed by setting the decimation/interpolation ratio to 1. 5 th order cic filter the next stage is a fifth order cascaded integrator comb (cic5) filter whose response is defined by the decimation rate. the purpose of these filters is to reduce the data rate to the final filter stage so that it can calculate more taps per output. ram coefficient filter the rcf stage is a sum-of-products fir filter with programmable 20-bit coefficients, and decimation rates programmable from 1 to 256 (1-32 in practice). each ram coefficient fir filter (rcf in figure 1) can handle a maximum of 160 taps. two or more rcf stages may be combined using flexible channel configuration to increase the processing power beyond the 160 tap maximum. the rcf outputs of each channel are directly routed to both output port multiplexers. the output multiplexer can route any of the four channels to the parallel outputs or link outputs.
preliminary technical data AD6652 rev. pra 9/16/2002 31 interpolating half-band filters and agc processed rcf data may also be routed to two half-band interpolation stages where up to four channels may be combined (interleaved), interpolated by a factor of two and agc (automatic gain control) applied. each agc stage has a dynamic range of 96.3 db. these half-band filters and agc stages can be bypassed independently of each other. the outputs from the two agc stages are routed to both output port multiplexers. each output has a ?link? port to permit seamless data interface with dsp devices such as the tigersharc tm. . a multiplexer for each port selects one of the six data sources to appear at the device parallel or link output pins. the overall filter response for the AD6652 is the composite of all decimating and interpolating stages. each successive filter stage is capable of narrower transition bandwidths but requires a greater number of dclk cycles to calculate the output. more decimation in the first filter stage will minimize overall power consumption. figure 28 illustrates the basic function of the AD6652: that is, to select and filter a single channel from a wide input spectrum. the frequency translator ?tunes? the desired carrier to base band. figure 29 shows the combined filter response of the rcic2, cic5, and rcf. dc fs/16 fs/8 3fs/16 fs/4 5fs/16 3fs/8 wideband input spectrum (-fsamp/2 to fsamp/2) signal of interest after frequency translation dc -fs/16 -fs/8 -3fs/16 -fs/4 -5fs/16 -3fs/8 signal of interest "image" dc fs/16 fs/8 3fs/16 fs/4 5fs/16 3fs/8 dc -fs/16 -fs/8 -3fs/16 -fs/4 -5fs/16 -3fs/8 fs/2 -fs/2 -fs/2 fs/2 nco "tunes" signal to wideband input spectrum (e.g. 30mhz from h ighspeed adc) f requency translation (e.g. single 1mhz channel tuned to basband ) figure 28. AD6652 frequency translation of wideband input spectrum
preliminary technical data AD6652 rev. pra 9/16/2002 32 figure 29. composite filter response of rcic2, cic5, and rcf memory mapping and address notation for the remainder of this document, frequent text references will be made to programming registers and memory mapping. the reader is advised to become familiar with the ?microport control? section, now, to gain an overview of the AD6652 register/memory mapping structure. all register addresses beginning with 0x indicate that the address characters that follow are in hexadecimal notation. a colon following an address indicates which bit(s), in decimal format, is/are involved. receive input matrix the receive signal processor stages feature dual high-speed crossbar-switched input ports that allow the most flexibility in routing the two adc data streams to the four receive processing channels. these can be diversity inputs or truly independent inputs such as separate antenna segments. crossbar switching means that any of the four processing channels may receive data from either port a or port b for a total of 16 possible combinations as seen in table iii below. input port routing is selected in each ncos control register at 0x88:6. ch 3 ch 2 ch 1 ch0 a a a a a a a b a a b a a a b b a b a a a b a b a b b a a b b b b a a a b a a b 1.5 . . . .
preliminary technical data AD6652 rev. pra 9/16/2002 33 b a b a b a b b b b a a b b a b b b b a b b b b table iii. crossbar-switched routing of the two 12-bit adc data streams (a & b) using the rsp input matrix rsp data latency the overall signal path latency from rsp input to output can be expressed in high-speed clock cycles. the equation below can be used to calculate the latency. () + + + = =
preliminary technical data AD6652 rev. pra 9/16/2002 34 amplitude dither amplitude dither can also be used to improve spurious performance of the nco. amplitude dither is enabled by setting bit 2 of 0x88. amplitude dither improves performance by randomizing the amplitude quantization errors within the angular to cartesian conversion of the nco. this option may reduce spurs at the expense of a slightly raised noise floor. amplitude dither and phase dither can be used together, separately or not at all. clear phase accumulator on hop when bit 3 is set, the nco phase accumulator is cleared prior to a frequency hop. this ensures a consistent phase of the nco on each hop. the nco phase offset is unaffected by this setting. if phase continuous hopping is desired, this bit should be cleared and the last phase in the nco phase register will be the beginning phase for the new frequency. reserved bits 4 and 5 are reserved and should written to logic 0. input select bit 6 of nco control register at address 0x88 controls input port selection. if this bit is set high, then input port b is connected to the selected filter channel. if this bit is cleared, then input port a is connected to the selected filter channel. sync pin select bits 7 and 8 of the nco control register determine which external sync pin (if any) is assigned to the channel of interest. the AD6652 has four sync pins: synca, syncb, syncc, and syncd. any of these sync pins can be assigned to any or all of the four receiver channels of the AD6652; however, a channel may have only one sync pin assigned to it. the sync pin(s) must also be enabled in the pin_sync control register at address 4 of the external memory map. table iv shows bit values to select a specific external sync pin. a address/bit 0x88:8 address/bit 0x88:7 selected sync pin 0 0 synca 0 1 syncb 1 0 syncc 1 1 syncd table iv. programming channel address register (car) bits to choose a sync pin for a selected nco. 2 nd order rcic filter the rcic2 filter is a second order cascaded re-sampling integrator comb filter. the resampler is implemented using a unique technique, which does not require the use of a high-speed clock, thus simplifying the design and saving power. the re-sampler allows for non-integer relationships between the master clock and the output data rate. this allows easier implementation of systems that are either multi-mode or require a master clock that is not a multiple of the data rate to be used. interpolation up to 512 and decimation up to 4096 is allowed in the rcic2. the re-sampling factor for the rcic2 (l) is a 9-bit integer. when combined with the decimation factor m, a 12-bit number, the total rate-change can be any fraction in the form of: m l r rcic = = ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ?
preliminary technical data AD6652 rev. pra 9/16/2002 35 2 2 2 2 sin sin 2 1 ) ( 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? + = ( ) ? = = =
preliminary technical data AD6652 rev. pra 9/16/2002 36 ratio of 0.25. thus any integer combination of l/m that yields 0.25 will work (1/4, 2/8 or 4/16). however, for the best dynamic range, the simplest ratio should be used. for example, ? gives better performance than 4/16. m rcic2 / l rcic2 -50db -60db -70db -80db -90db -100db 2 1.79 1.007 0.566 0.318 0.179 0.101 3 1.508 0.858 0.486 0.274 0.155 0.087 4 1.217 0.696 0.395 0.223 0.126 0.071 5 1.006 0.577 0.328 0.186 0.105 0.059 6 0.853 0.49 0.279 0.158 0.089 0.05 7 0.739 0.425 0.242 0.137 0.077 0.044 8 0.651 0.374 0.213 0.121 0.068 0.038 9 0.581 0.334 0.19 0.108 0.061 0.034 10 0.525 0.302 0.172 0.097 0.055 0.031 11 0.478 0.275 0.157 0.089 0.05 0.028 12 0.439 0.253 0.144 0.082 0.046 0.026 13 0.406 0.234 0.133 0.075 0.043 0.024 14 0.378 0.217 0.124 0.07 0.04 0.022 15 0.353 0.203 0.116 0.066 0.037 0.021 16 0.331 0.19 0.109 0.061 0.035 0.02 table v ssb rcic2 alias rejection table (f samp = 1) bandwidth shown in percentage of f samp. decimation and interpolation registers rcic2 decimation values are stored in register 0x90. this register is a 12-bit register and contains the decimation portion less 1. the interpolation portion is stored in register 0x91. this 9-bit value holds the interpolation less one. rcic2 scale register register 0x92 contains the scaling information for this section of the circuit. the primary function is to store the scale value computed in the sections above. bits 4-0 of this register should be written with the same values of those written to bits 9-5 to accommodate an redundant internal hardware feature. bits 9-5 (srcic2) contain the 5-bit scaling factor for rcic2. bit 10 of this register is reserved and must be written low. bit 11 of this register is reserved and must be written low. in applications that do not require the features of the rcic2, it may be by-passed by setting the l/m ratio to 1/1. this effectively bypasses all circuitry of the rcic2 except the scaling which is still effectual. 5 th order cic filter the fourth signal processing stage, cic5, implements a sharper fixed-coefficient, decimating filter than rcic2. the input rate to this filter is f samp2 . the maximum input rate is given by the equation below. n ch equals two for diversity channel real input mode; otherwise n ch equals one. in order to satisfy this equation, m rcic2 can be increased, n ch can be reduced, or f clk can be increased (reference fractional rate input timing described in the ?input timing? section). ch clk samp n f f =? ? ? ? ? ? ? ? ? + ? ? =? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ( ) ( ) ? ? = ( ) ? = +
preliminary technical data AD6652 rev. pra 9/16/2002 37 f f m samp samp cic 5 2 5 =
preliminary technical data AD6652 rev. pra 9/16/2002 38 rcf filter length the maximum number of taps this filter can calculate, n taps , is given by the equation below. the value n taps -1 is written to the channel register within the AD6652 at address 0xa2. ? ? ? ? ? ? ? ? ? = () ? =
preliminary technical data AD6652 rev. pra 9/16/2002 39 if bit 7 is set, the same exponent will be used for both the real and imaginary (i and q) outputs. the exponent used will be the one that prevents numeric overflow at the expense of small signal accuracy. however, this is seldom a problem as small numbers would represent 0 regardless of the exponent used. bit 8 is the rcf bank select bit used to program the register. when this bit is 0, the lowest block of 128 is selected (taps 0 through 127). when high, the highest block is selected (taps 128 thro ugh 255). it should be noted that while the chip is computing filters, tap 127 is adjacent to 128 and there are no paging issues. bit 9 selects where the input to each rcf originates. if bit 9 is clear, then the rcf input comes from the cic5 normally associated with the rcf. if however, the bit is set, then the input comes from cic5 channel 1. the only exception is channel 1, which uses the output of cic5 channel 0 as its alternate. using this feature, each rcf can either operate on its own channel data or be paired with the rcf of channel 1. the rcf of channel 1 can also be pared with channel 0. this control bit is used with poly- phase distributed filtering. if bit 10 is clear, the AD6652 channel operates in normal mode. however, if bit 10 is set, then the rcf is bypassed to channel bist. see bist (built in self test) section for more details. interpolating half band filters the AD6652 has two interpolating half band finite impulse response filters that immediately precede the two digital agcs and after the four rcf channel outputs. each interpolating half band takes 16-bit i and 16-bit q data from the preceding rcf and outputs 16-bit i and 16-bit q to the agc. the half band and agc operate independently of each other, so the agc can be bypassed, in which case the output of the half band is sent directly to the output data port. the half bands also operate independent of each other -- either one can be enabled or disabled. the control register for half band a is at address 0x08 and for half band b is at address 0x09. halfband filters also perform the function of interleaving data from various rcf channel outputs prior to the actual function of interpolation. this interleaving of data is allowed even when the actual function of halfband filter is bypassed. this feature allows for the usage of multiple channels (implementing a polyphase filter) on the AD6652 to process a single carrier. either rcf phase decimation of the start hold-off counter for the channels are used to process one cdma2000 carrier, rcf filters for both the channels should be 180 o out of phase. this can be done using rcf phase decimation or an appropriate start hold- off counter followed by appropriate nco phase offsets. half band a can listen to all 4 channels: channels 0, 1, 2, and 3; channel 0 and 1; or only channel 0. half band b can listen to channels 2 and 3,or only channel 2. each half band interleaves the channels specified in its control register and interpolates by two on the combined data from those channels. for one channel running at twice the chip rate, the halfband can be used to output channel data at 4x the chip rate.the frequency response of the interpolating halfband fir is shown in figure 31. db 0 0.5 1 1.5 2 2.5 3 3.5 4 80 70 60 50 40 30 20 10 0 spectrum of halfband multiples of chip rate figure 31. interpolating halfband frequency response the snr of the interpolating halfband is around ?149.6 db. the highest error spurs due to fixed-point arithmetic are around ?172.9 db. the coefficients of the 13-tap interpolating halfband fir are given in the table ix. 0 14 0 -66 0 309 512 309 0 -66 0 14 0
preliminary technical data AD6652 rev. pra 9/16/2002 40 tableix. halfband coefficients automatic gain control the AD6652 is equipped with two independent automatic gain control (agc) loops for direct interface with a rake receiver. each agc circuit has 96db of range. it is important that the decimating filters of the AD6652 preceding the agc reject undesired signals, so that each agc loop is only operating on the carrier of interest and carriers at other frequencies do not affect the ranging of the loop. the agc compresses the 23-bit complex output from the interpolating half band filter into a programmable word size of 4-8, 10, 12 or 16 bits. since the small signals from the lower bits are pushed in to higher bits by adding gain, the clipping of the lower bits does not compromise the snr of the signal of interest. the agc maintains a constant mean power on the output despite the level of the signal of interest, allowing operation in environments where the dynamic range of the signal exceeds the dynamic range of the output resolution. the agc and the interpolation filters are not tied together and any one or both of them can be selected without the other. the agc section can be bypassed if desired, by setting bit 0 of the agc control word. when bypassed the i/q data is still clipped to a desired number of bits and a constant gain can be provided through the agc gain multiplier. there are three sources of error introduced by the agc function: underflow, overflow, and modulation. underflow is caused by truncation of bits below the output range. overflow is caused by clipping errors when the output signal exceeds the output range. modulation error occurs when the output gain varies during the reception of a data. the desired signal level should be set based on the probability density function of the signal so that the errors due to underflow and overflow are balanced. the gain and damping values of the loop filter should be set so that the agc is fast enough to track long term amplitude variations of the signal that might cause excessive underflow or overflow, but slow enough to avoid excessive loss of amplitude information due to the modulation of the signal. the agc loop the agc loop is implemented using a log-linear architecture. it contains four basic operations: power calculation, error calculation, loop filtering and gain multiplication. the agc can be configured to operate in one of the two modes: desired signal level mode or desired clipping level mode as set by bit 4 of agc control word (0x0a, 0x12). the agc adjusts the gain of the incoming data according to how far it is from a given desired signal level or desired clipping level, depending on the mode of operation selected. two data paths to the agc loop are provided: one, before the clipping circuitry and one after the clipping circuitry as shown in figure 34. for desired signal level mode, only the i/q path from before the clipping is used. for desired clipping level mode, the difference of the i/q signals from before and after the clipping circuitry is used. desired signal level mode in this mode of operation, the agc strives to maintain the output signal at a programmable set level. this mode of operation is selected by putting a value of zero in bit 4 of agc control word (0x0a, 0x12). first, the loop finds the square (or power) of the incoming complex data signal by squaring i and q and adding them. this operation is implemented in exponential domain using 2 x (power of 2). the agc loop has an average and decimate block. this average and decimate operation takes place on power samples and before the square root operation. this block can be programmed to average 1-16384 power samples and the decimate section can be programmed to update the agc once every 1-4096 samples. the limitation on the averaging operation is that the number of averaged power samples should be a multiple of the decimation value (1x, 2x, 3x or 4x times). the averaging and decimation effectively means the agc can operate over averaged power of 1-16384 output samples. the choice of updating the agc once every 1- 4096 samples and operating on average power facilitates the implementation of loop filter with slow time constants, where the agc error converges slowly and makes infrequent gain adjustments. it would also be useful in scenarios where the user wants to keep the gain scaling constant over a frame of data (or a stream of symbols). due to the limitation on the number of average samples to be a multiple of decimation value, only the multiple number 1, 2, 3 or 4 is programmed. this number is programmed in bits 1,0 of 0x10 and 0x18 registers. these averaged samples are then decimated with decimation ratios programmable from 1 to 4096. this decimation ratio is defined in 12-bit registers 0x11 and 0x19.
preliminary technical data AD6652 rev. pra 9/16/2002 41 x i q x 2 x power of 2 'p' pole 'r' desired mean square (i + jq) + log 2 (x) i q clip clip 23 bits programmable bit width - - () ? ? + ? + ? ? () ? ? ? + ? ? = ? = ? ? ? ? ? ? ? = ? ? ? + + ? =
preliminary technical data AD6652 rev. pra 9/16/2002 42 if the agc is properly configured (in terms of offset in request level) then there are no gains except the filter gain k. under these circumstances a closed loop expression for the agc loop is possible and is given by 2 1 1 ) 1 ( 1 ) ( 1 ) ( ) ( ? ? ? + ? ? + = + = ? ? + + ? + = ? ? ? ? ? ? ? ? = =
preliminary technical data AD6652 rev. pra 9/16/2002 43 signal level. the desired clipping level mode can be selected by setting the bit 4of individual agc control words (0x0a, 0x12). for signals that tend to exceed the bounds of the peak-to-average ratio, desired clipping level option allows a way to keep from truncating those signals and still provide an agc that attacks quickly and settles to the desired output level. the signal path for this mode of operation is shown with broken arrows in the block diagram and the operation is similar to the desired signal level mode. first, the data from the gain multiplier is truncated to a lower resolution (4, 5, 6, 7, 8, 10, 12, or 16 bits) as set by the agc control word. an error term (both i and q) is generated that is the difference between the signals before and after truncation. this term is passed to the complex squared magnitude block, for averaging and decimating the update samples and taking their square root to find rms samples as in desired signal level mode. in place of the request desired signal level, a desired clipping level is subtracted, leaving an error term to be processed by the second order loop filter. the rest of the loop operates the same way as the desired signal level mode. this way the truncation error is calculated and the agc loop operates to maintain a constant truncation error level. apart from bit 4 of the agc control words, the only register setting changes compared to the desired signal level mode is that the desired clipping level is stored in the agc desired level registers (0x0c, 0x15) instead of the request signal level (as in desired signal level mode). synchronization in scenarios where agc output is connected to a rake receiver, the rake receiver can synchronize the average and update section to update the average power for agc error calculation and loop filtering. this external sync signal synchronizes the agc changes to rake receiver and makes sure that the agc gain word does not change over a symbol period and hence more accurate estimation. such synchronization can be accomplished by setting the appropriate bits of the agc control register. when the channel comes out of sleep, it loads the agc hold off counter value and starts counting down, clocked by the master clock. when this counter reaches zero, the cic filter of the agc starts decimation and updates the agc loop filter based on the cic decimation value set. further whenever the user wants to synchronize the start of decimation for a new update sample an appropriate hold- off value can be set in agc hold-off counter (0x0b, 0x13) and the sync now bit (bit 3) in the agc control word is set. upon setting this bit the hold-off counter value is counted down and a cic decimated value is updated on the count of zero. along with updating a new value, the cic filter accumulator can be reset if init on sync bit (bit 2) of the agc control word is set. each sync will initiate a new sync signal unless first sync only bit (bit 1) of the agc control word is set. if this bit is not set, again the hold-off counter is loaded with the value in the hold-off register to count down and repeat the same process. these additional features make the agc synchronization more flexible and applicable to varied circumstances. addresses 0x0a ? 0x11 have been reserved for configuring agc a and addresses 0x12 ? 0x19 have been reserved for configuring agc b. the register specifications are detailed in the ?memory map for output port control registers? section of this data sheet. user configurable built in self test (bist) the AD6652 includes two built in test features to test the integrity of each channel. the first is a ram bist (built in self test) and is intended to test the integrity of the high-speed random access memory within the AD6652. the second is channel bist, which is designed to test the integrity of the main signal paths of the AD6652. each bist function is independent of the other meaning that each channel can be tested independently at the same time. ram bist the ram bist can be used to validate functionality of the on-chip ram. this feature provides a simple pass/fail test, which will give confidence that the channel ram is operational. the following steps should be followed to perform this test. ? ? ? ?
preliminary technical data AD6652 rev. pra 9/16/2002 44 000 pass pass 010 fail pass 100 pass fail 110 fail fail table x8. bist register 0xa8 channel bist the channel bist is a thorough test of the selected AD6652 signal path. with this test mode, it is possible to use externally supplied vectors or an internal pseudo- random generator. an error signature register in the rcf monitors the output data of the channel and is used to determine if the proper data exits the rcf. if errors are detected then each internal block may be bypassed and another test can be run to debug the fault. the i and q paths are tested independently. the following steps should be followed to perform this test. ? ? ? ? ? ? ? ? ? ? ? ?
preliminary technical data AD6652 rev. pra 9/16/2002 45 2. set the sleep bits low (ext address 3). this enables the channel. the channel must the sleep mode low to activate a channel. start with soft sync the AD6652 includes the ability to synchronize channels or chips under microprocessor control. one action to synchronize is the start of channels or chips. the start update hold off counter (0x83) in conjunction with the start bit and sync bit (ext address 5) allow this synchronization. basically the start update hold off counter delays the start of a channel(s) by its value (number of AD6652 clks. the following method is used to synchronize the start of multiple channels via microprocessor control. 1. set the appropriate channels to sleep mode (a hard reset to the AD6652 reset pin brings all 4 channels up in sleep mode). 2. note that the time from when the rdy (pin 57) goes high to when the nco begins processing data is the contents of the start update hold off counter(s) (0x83) + 6 master clock cycles. 3. write the start update hold off counter(s) (0x83) to the appropriate value (greater than 1 and less than 2^16-1). if the chip(s) is not initialized, all other registers should be loaded at this step. 4. write the start bit and the sync bit high (ext address 5). 5. this starts the start update hold off counter counting down. the counter is clocked with the AD6652 dclk signal. when it reaches a count of one the sleep bit of the appropriate channel(s) is set low to activate the channel(s). start with pin sync the AD6652 has 4 sync pins a, b, c and d that can be used to provide for very accurate synchronization channels. each channel can be programmed to look at any of the 4 sync pins. additionally, any or all channels can monitor a single sync pin or each can monitor a separate pin, providing complete flexibility of synchronization. synchronization of start with one of the external signal is accomplished with the following method. 1. set the appropriate channels to sleep mode (a hard reset to the AD6652 reset pin brings all 4 channels up in sleep mode). 2. note that the time from when the sync pin goes high to when the nco begins processing data is the contents of the start update hold off counter(s) (0x83) + 3 master clock cycles. 3. write the start update hold off counter(s) (0x83) to the appropriate value (greater than 1 and less than 2^16-1). if the chip(s) is not initialized, all other registers should be loaded at this step. 4. set the start on pin sync bit and the appropriate sync pin enable high (ext address 4 ) (a, b, c or d). 5. when the sync pin is sampled high by the AD6652 dclk this enables the count down of the start update hold off counter. the counter is clocked with the AD6652 dclk signal. when it reaches a count of one the sleep bit of the appropriate channel(s) is set low to activate the channel(s). hop hop is a jump from one nco frequency to a new nco frequency. this change in frequency can be synchronized via microprocessor control (soft sync) or an external sync signal (pin sync) as described below. to set the nco frequency without synchronization the following method should be used. set freq no hop 1. set the nco freq hold off counter to 0. 2. load the appropriate nco frequency. the new frequency will be immediately loaded to the nco. hop with soft sync the AD6652 includes the ability to synchronize a change in nco frequency of multiple channels or chips under microprocessor control. the nco freq hold off counter (0x84) in conjunction with the hop bit and the sync bit (ext address 4) allow this synchronization. basically the nco freq hold off counter delays the new frequency from being loaded into the nco by its value (number of AD6652 clks). the following method is used to synchronize a hop in frequency of multiple channels via microprocessor control. 1. note that the time from when the rdy (pin 57) goes high to when the nco begins processing data is the contents of the nco freq hold off counter (0x84) + 7 master clock cycles. 2. write the nco freq hold off (0x84) counter to the appropriate value (greater than 1 and less then 2^16- 1). 3. write the nco frequency register(s) to the new desired frequency. 4. write the hop bit and the sync(s) bit high (ext address 4). 5. this starts the nco freq hold off counter counting down. the counter is clocked with the AD6652 dclk signal. when it reaches a count of one the new frequency is loaded into the nco.
preliminary technical data AD6652 rev. pra 9/16/2002 46 hop with pin sync the AD6652 include 4 sync pins to provide the most accurate synchronization, especially between multiple AD6652s. synchronization of hopping to a new nco frequency with an external signal is accomplished with the following method. 1. note that the time from when the sync pin goes high to when the nco begins processing data is the contents of the nco freq hold off counter (0x84) + 5 master clock cycles. 2. write the nco freq hold off counter(s) (0x84) to the appropriate value (greater than 1 and less than 2^16- 1). 3. write the nco frequency register(s) to the new desired frequency. 4. set the hop on pin sync bit and the appropriate sync pin enable high. 5. when the selected sync pin is sampled high by the AD6652 dclk this enables the count down of the nco freq hold off counter. the counter is clocked with the AD6652 dclk signal. when it reaches a count of one the new frequency is loaded into the nco. parallel output ports the AD6652 incorporates two independent 16-bit parallel ports for output data transfer. to minimize package ball count, the eight lsbs of each 16-bit port are shared with their respective dsp link port data bits (see figure 34). this means that an output port can transmit 16-bit parallel data or 8-bit link port data, but not both. transmitting both link and parallel data simultaneously requires that the second AD6652 output port be configured for that purpose. each parallel output port has six data sources routed to it (see front page ?functional block diagram?): ? ? ?
preliminary technical data AD6652 rev. pra 9/16/2002 47 the parallel ports are enabled by setting bit 7 of the link control registers at addresses 0x19 and 0x1b for ports a and b, respectively.each parallel port is capable of operating in either channel mode or agc mode. each mode is described in detail below. channel mode parallel port channel mode is selected by setting bit 0 of addresses 0x18 and 0x1a for parallel ports a and b, respectively. in channel mode, i and q words from each channel is directed to the parallel port, bypassing the agc. the specific channels output by the port is selected by setting bits 1 through 4 of input port control register 0x18 (port a) and 0x1a (port b). channel mode provides two data formats. each format requires a different number of parallel port clock (pclk) cycles to complete the transfer of data. in each case, each data element is transferred during one pclk cycle. see figures 35 and 36, which present channel mode parallel port timing. pclk t dpreq pxreq pxack t dpp px[15:0] i[15:0] q[15:0] pxiq t dpiq pxch[1:0] pxch[1:0] = channel # t dpch figure 35. channel mode interleaved format. px[15:0] pclk t dpreq pxreq pxack t dpp i[15:8], q [7:0] pxiq t dpiq pxch[1:0] pxch [1:0] = channel # t dpch figure 36. channel mode 8i/8q parallel format. the 16-bit interleaved format provides i and q data for each output sample on back-to-back pclk cycles. both i and q words consist of the full port width of 16 bits. data output is triggered on the rising edge of pclk when both req and ack are asserted. i data is output during the first pclk cycle; and the paiq and pbiq output indicator pins are set high to indicate that i data is on the bus. q data is output during the subsequent pclk cycle; and the paiq and pbiq output indicator pins are low during this cycle. the 8-bit concurrent format provides 8 bits of i data and 8 bits of q data simultaneously during one pclk cycle, also triggered on the rising edge of pclk. the i byte occupies the most significant byte of the port, while the q byte occupies the least significant byte. the paiq and pbiq output indicator pins are set high during the pclk cycle. note that if data from multiple channels are output consecutively, the paiq and pbiq output indicator pins will remain high until data from all channels has been output. the pach[1:0] and pbch[1:0] pins provide a 2-bit binary value indicating the source channel of the data currently being output. care should be taken to read data from the port as soon as possible. if not, the sample will be overwritten when the next new data sample arrives. this occurs on a per- channel basis; i.e., a channel 0 sample will only be overwritten by a new channel 0 sample, etc. the order of data output is dependent on when data arrived at the port, which is is a function of total decimation rate, start-holdoff values, etc. priority order is, from highest to lowest, channels 0, 1, 2, 3.
preliminary technical data AD6652 rev. pra 9/16/2002 48 agc mode parallel port channel mode is selected by clearing bit 0 of addresses 0x18 and 0x1a for parallel ports a and b, respectively. i and q data output in agc mode are output from the agc, not the individual channels. each agc receives data from only two AD6652 channels; agc a accepts data from channels 0 and 1, while agc b accepts data from channels 2 and 3. each pair of channels is required to be configured such that the generation of output samples from the channels is out of phase (by typically 180 degrees). each parallel port can provide data from either one or both agcs. bits 1 and 2 of register addresses 0x18 (port a) and 0x1a (port b) control the inclusion of data from agcs a and b, respectively. agc mode provides only one i&q format, which is similar to the 16-bit interleaved format of channel mode. when both req and ack are asserted, the next rising edge of pclk triggers the output of a 16-bit agc i word for one pclk cycle. the paiq and pbiq output indicator pins are high during this cycle, and is low otherwise. a 16 bit agc q word is provided during the subsequent pclk cycle. if the agc gain word has been updated since the last sample, a 16-bit gain word is provided during the pclk cycle following the q word. the data provided by the pach[1:0] and pbch[1:0] pins in agc mode is different than that provided in channel mode. in agc mode, pach[0] and pbch[0] indicate the agc source of the data currently being output (0=agc a, 1=agc b). pach[1] and pbch[1] indicate whether the current data is and i/q word or an agc gain word (0=i/q word, 1=agc gain word). the two agc modes are shown below in figures 39 and 40. pclk t dpreq pxreq pxack t dpp px[15:0] i[15:0] q[15:0] pxiq t dpiq pxch[1:0] pxch[0] = agc # pxch[1] = 0 t dpch figure 37. agc with no gain word. pclk pxreq pxack px[15:0] t dpreq t dpp i[15:0] q[15:0] pxiq t dpiq gain[15:0] pxch[1:0] pxch[0] = agc# pxch[1] = 0 pxch[0] = agc# pxch[1] = 1 t dpch figure 38. agc with gain word. master/slave pclk modes the parallel ports may operate in either master or slave mode. the mode is set via the port clock control register (address 0x1c). the parallel ports power up in slave mode to avoid possible contentions on the pclk pin. in master mode, pclk is an output whose frequency is the AD6652 clock frequency divided by the pclk divisor. since values for pclk_divisor[2:1] can range from 0 to 3, integer divisors of 1 to 4, respectively, can be obtained. since the maximum clock rate of the AD6652 is 65 mhz, the highest plck rate in master mode is also 65 mhz. master mode is selected by setting bit 0 of address 0x1c. in slave mode, external circuitry provides the pclk signal. slave-mode pclk signals may be either synchronous or asynchronous. the maximum slave-mode pclk frequency is 100 mhz. parallel port pin functionality the following describes the functionality of the pins used by the parallel ports. pclk: input/output. as an output (master mode), the maximum frequency is dclk/n, where dclk is AD6652 clock and n is an integer divisor from 1 to 4. as an input (slave mode), it may be asynchronous relative to the AD6652 dclk. this pin powers up as an input to avoid possible contentions. other port outputs change on the rising edge of pclk. req: active high output, synchronous to pclk. a logic high on this pin indicates that data is available to be shifted out of the port. a logic high value remains high until all pending data has been shifted out. ack: active high asynchronous input. applying a logic low on this pin inhibits parallel port data shifting.
preliminary technical data AD6652 rev. pra 9/16/2002 49 applying a logic high to this pin when req is high causes the parallel port to shift out data according the programmed data mode. ack is sampled on the rising edge of pclk. assuming req is asserted, the latency from the assertion of ack to data appearing at the parallel port output is no more than 1.5 pclk cycles (see figure 13). ack may be held high continuously; in this case, when data becomes available, shifting begins 1 pclk cycle after the assertion of req (see figure 37). paiq, pbiq: high whenever i data is present on the port output, low otherwise. pach[1:0], pbch[1:0]: these pins serve to identify data in both of the data modes. in channel mode, these pins form a 2-bit binary number identifying the source channel of the current data word. in agc mode, [0] indicates the agc source (0=agc a, 1=agc b), and [1] indicates whether the current data word is i/q data (0) or a gain word (1). pa[15:0], pb[15:0]: parallel output data ports. contents and format are mode-dependent. link port the AD6652 has two configurable link ports that provide a seamless data interface with the tigersharc dsp. each link port allows the AD6652 to write output data to the receive dma channel in the tigersharc for transfer to memory. since they operate independently of each other, each link port can be connected to a different tigersharc or different link ports on the same tigersharc. the figure 39 below shows how to connect one of the two AD6652 link ports to one of the four tigersharc link ports. link port a is configured through register 0x19 and link port b is configured through register 0x1b. ad6634 lclkin lclkout ldat pclk tigersharc lclkin lclkout ldat pclk 8 figure 39. link port connection between AD6652 and tigersharc link port data format each link port can output data to the tigersharc in 5 different formats: 2 channel, 4 channel, dedicated agc, redundant agc with gain, and redundant agc without gain. each format outputs 2 bytes of i data and 2 bytes of q data to form a 4 byte iq pair. since the tigersharc link port transfers data in quad-word (16-byte) blocks, four iq pair can make up one quad-word. if the channel data is selected (bit 0 = 0), then 4-byte iq words of the four channels can be output in succession or alternating channel pair iq words can be output. the following figures 40 and 41 show the quad-word transmitted for each scenario with corresponding register values for configuring each link port. ch 3 i,q (4 bytes) ch 2 i,q (4 bytes) ch 1 i,q (4 bytes) ch 0 i,q (4 bytes) link port a or b addr 0x19 or 0x1a bit 0=0, bit 1=0 ch 1 i,q (4 bytes) ch 0 i,q (4 bytes) ch 1 i,q (4 bytes) ch 0 i,q (4 bytes) link port a ch 3 i,q (4 bytes) ch 2 i,q (4 bytes) ch 3 i,q (4 bytes) ch 2 i,q (4 bytes) link port b addr 0x19 and 0x1a bit 0=0, bit 1=1 figure 40. link port data from rcf if agc output is selected (bit 0 = 1), then gain information can be sent with the iq pair from each agc. each link port can be configured to output data from one agc or both link ports can output data from the same agc. if both link ports are transmitting the same data, then gain data must be sent with the iq words (bit 2 = 0). note that the actual agc gain is only 2 bytes, so the link port sends 2 bytes of 0?s immediately after each gain word to make a full 16-byte quad-word. agc b iq (4 bytes) agc a i,q (4 bytes) agc b iq (4 bytes) agc a i,q (4 bytes) link port a or b addr 0x19 or 0x1a bit 0=1, bit 1=0, bit 2=0 agc b gain (4 bytes) agc b i,q (4 bytes) agc a gain (4 bytes) agc a i,q (4 bytes) link port a or b addr 0x19 or 0x1a bit 0=1, bit 1=0, bit 2=1 agc a gain (4 bytes) agc a i,q (4 bytes) agc a gain (4 bytes) agc a i,q (4 bytes) link port a agc b gain (4 bytes) agc b i,q (4 bytes) agc b gain (4 bytes) agc b i,q (4 bytes) link port b addr 0x19 and 0x1a bit 0=1, bit 1=1, bit 2=0 figure 41. link port data from agc
preliminary technical data AD6652 rev. pra 9/16/2002 50 note that bit 0 =1 bit 1 = 0, and bit 2 = 1 is not a valid configuration. bit 2 must be set to 0, to output agc a iq and gain words on link port a and agc b iq and gain words on link port b. link port timing both link ports run off of pclk, which can be externally provided to the chip (addr 0x1c bit 0 = 0) or generated from the master clock of the AD6652 (addr 0x1c bit 0 = 1). this register boots to 0 (slave mode) and allows the user to control the data rate coming from the AD6652. pclk can be run as fast as 100 mhz. the link port provides a 1-byte data words (la[7:0], lb[7:0] pins) and output clocks (laclkout, lbclkout pins) in response to a ready signals (laclkin, lbclkin pins) from the receiver. each link port transmits 8 bits on each edge of lclkout, requiring 8 lclkout cycles to complete transmission of the full 16 bytes of a tigersharc quad-word. lclkin tigersharc ready to receive next quad-word tigersharc ready to receive quad-word lclkout wait >= 6 cycles next quad-word ldat [7:0] d0 d1 d2 d3 d4 d15 d0 d1 d2 figure 42. link port data transfer due to the tigersharc link port protocol, the AD6652 must wait at least 6 pclk cycles after the tigersharc is ready to receive data, as indicated by the tigersharc setting the respective AD6652 lclkin pin high. once the AD6652 link port has waited the appropriate number of pclk cycles and has begun transmitting data, the tigersharc does a connectivity check by sending the AD6652 lclkin low and then high while the data is being transmitted. this tells the AD6652 link port that the tigersharc?s dma is ready to receive the next quad- word after completion of the current quad-word. because the connectivity check is done in parallel to the data transmission, the AD6652 is able to stream uninterrupted data to the tigersharc. the length of the wait before data transmission is a 4-bit programmable value in the link port control registers (0x19 and 0x1b bits 6-3). this value allows the AD6652 pclk and the tigersharc pclk to be run at different rates and out of phase. ? ? ? ? ? ? ? ? ? ? ?
preliminary technical data AD6652 rev. pra 9/16/2002 51 81 soft_sync control register 2 1: hop 0: start 82 pin_sync control register 3 2: first sync only 1: hop_en 0: start_en 83 start hold-off counter 16 start hold-off value 84 nco frequency hold-off counter 16 nco_freq hold-off value 85 nco frequency register 0 16 nco_freq[15:0] 86 nco frequency register 1 16 nco_freq[31:16] 87 nco phase offset register 16 nco_phase[15:0] 88 nco control register 9 8-7: sync input select[1:0] 6: input port select b or a 5-4: reserved, write both bits logic low 3: clear phase accumulator on hop 2: amplitude dither 1: phase dither 0: by-pass (a-input -> i-path, b -> q) 89-8f unused table xii. initial channel address memory map listing 0x00-0x7f: coefficient memory(cmem) this is the coefficient memory(c-mem) used by the rcf. it is memory mapped as 128 words by 20 bits. a second 128 words of ram may be accessed via this same location by writing bit 8 of the rcf control register high at channel address 0xa4. the filter calculated will always use the same coefficients for i and q. by using memory from both of these 128 blocks a filter up to 160 taps can be calculated. multiple filters can be loaded and selected with a single internal access to the coefficient offset register at channel address 0xa3. 0x80: channel sleep register this register contains the sleep bit for the channel. when this bit is high then the channel is placed in a low power state. when this bit is low then the channel processes data. this bit can also be set by accessing the sleep register at external address 3. when the external sleep register is accessed then all four channels are accessed simultaneously and the sleep bits of the channels are set appropriately. 0x81: soft_sync register this register is used to initiate sync events through the micro port. if the hop bit is written high then the hop hold-off counter at address 0x84 is loaded and begins to count down. when this value reaches 1 then the nco frequency register used by the nco accumulator, is loaded with the data from channel addresses 0x85 and 0x86. when the start bit is set high then the start hold- off counter is loaded with the value at address 0x83 and begins to count down. when this value hits 1 then the sleep bit in address 0x80 is dropped low and the channel is started. 0x82: pin_sync register this register is used to control the functionality of the sync pins. any of the four sync pins can be chosen and monitored by the channel. the channel can be configured to initiate either a start or hop sync event by setting the hop or start bit high. these bits function as enables so that when a sync pulse occurs then either the start or hop hold-off counters are activated in the same manner as with a soft_sync. 0x83: start hold-off counter the start hold-off counter is loaded with the value written to this address when a start_sync is initiated. it can be initiated by either a soft_sync or pin_sync. the counter begins decrementing and when it reaches a value of 1 the channel is brought out of sleep and begins processing data. if the channel is already running then the phase of the filters are adjusted such that multiple AD6652s can be synchronized. a periodic pulse on the sync pin can be used in this way to adjust the timing of the filters with the resolution of the adc sample clock. if this register is written to a 1 then the start will occur immediately when the sync comes into the channel. if it is written to a 0 then no sync will occur. 0x84: nco frequency hold-off counter
preliminary technical data AD6652 rev. pra 9/16/2002 52 the nco frequency hold-off counter is loaded with the value written to this address when either a soft_sync or pin_sync comes into the channel. the counter begins counting down so that when it reaches 1 the nco frequency word is updated with the values of addresses 0x85 and 0x86. this is known as a hop or hop_sync. if this register is written to a 1 then the nco frequency will be updated immediately when the sync comes into the channel. if it is written to a 0 then no hop will occur. nco hops can be either phase continuous or non-phase continuous depending upon the state of bit 3 of the nco control register at channel address 0x88. when this bit is low then the phase accumulator of the nco is not cleared but starts to add the new nco frequency word to the accumulator as soon as the sync occurs. if this bit is high then the phase accumulator of the nco is cleared to 0 and the new word is then accumulated. 0x85: nco frequency register 0 this register represents the 16 lsbs of the nco frequency word. these bits are shadowed and are not updated to the register used for the processing until the channel is either brought out of sleep or a soft_sync or pin_sync has been issued. in the latter two cases the register is updated when the frequency hold-off counter hits a value of 1. if the frequency hold-off counter is set to 1 then the register will be updated as soon as the shadow is written. 0x86: nco frequency register 1 this register represents the 16 msbs of the nco frequency word. these bits are shadowed and are not updated to the register used for the processing until the channel is either brought out of sleep or a soft_sync or pin_sync has been issued. in the latter two cases the register is updated only when the frequency hold-off counter hits a value of 1. if the frequency hold-off counter is set to 1 then the register will be updated as soon as the shadow is written. 0x87: nco phase offset register this register represents a 16-bit phase offset to the nco. it can be interpreted as values ranging from 0 to just under 2
preliminary technical data AD6652 rev. pra 9/16/2002 53 93 reserved 8 reserved (must be written low) 94 cic5 decimation ?1 8 m cic5 -1 95 cic5 scale 5 4-0: cic5_scale[4:0] 96 reserved 8 reserved(must be written low) 97-9f unused a0 rcf decimation ? 1 8 m rcf -1 a1 rcf decimation phase 8 p rcf a2 rcf number of taps ?1 8 n taps -1 a3 rcf coefficient offset 8 co rcf a4 rcf control register 11 10: rcf by-pass bist 9: rcf input select (own 0, other 1) 8: program ram bank 1/0 7: use common exponent 6: force output scale 5-4: output format 1x: floating point 12+4 01: floating point 8+4 00: fixed point 3-0: output scale a5 bist signature for i path 16 bist-i a6 bist signature for q path 16 bist-q a7 # of bist outputs to accumulate 20 19-0: # of outputs(counter value read) a8 ram bist control register 3 2: d-ram fail/pass 1: c-ram fail/pass 0: ram bist enable a9 output control register 9: map rcf data to bist registers 5: output format 1: 16-bit i and 16-bit q 0: 12-bit i and 12-bit q table xiii. conclusion of the channel address memory map 0x90: rcic2 decimation ? 1 (m rcic2 -1) this register is used to set the decimation in the rcic2 filter. the value written to this register is the decimation minus one. the rcic2 decimation can range from 1 to 4096 depending upon the interpolation of the channel. the decimation must always be greater than the interpolation. m rcic2 must be chosen larger than l rcic2 and both must be chosen such that a suitable rcic2 scalar can be chosen. for more details the rcic2 section should be consulted 0x91: rcic2 interpolation ? 1 (l rcic2 -1) this register is used to set the interpolation in the rcic2 filter. the value written to this register is the interpolation minus one. the rcic2 interpolation can range from 1 to 512 depending upon the decimation of the rcic2. there is no timing error associated with this interpolation. see the rcic2 section of the data sheet for further details. 0x92: rcic2 scale the rcic2 scale register is used to provide attenuation to compensate for the gain of the rcic2 and to adjust the linearization of the data from the floating-point input. the use of this scale register is influenced both by the rcic2 growth and floating point input port considerations. the rcic2 section should be consulted for details. the rcic2 scalar has been combined with the exponent offset and will need to be handled appropriately in both the input port and rcic2 sections. bit 11 determines the polarity of the exponent. normally, this bit will be cleared unless and adc such as the ad6600 is used, in which case this bit will be set. bit 10 determines the weight of the exponent word associated with the input port. when this bit is low then each exponent step is considered to be worth 6.02db. when this bit is high then each exponent step is considered to be worth 12.02db.
preliminary technical data AD6652 rev. pra 9/16/2002 54 bits 9-5 are the actual scale value used when the level indicator, li pin associated with this channel is active. bits 4-0 are the actual scale value used when the level indicator, li pin associated with this channel is active. 0x93: reserved (must be written low) 0x94: cic5 decimation ? 1 (m cic5 -1) this register is used to set the decimation in the cic5 filter. the value written to this register is the decimation minus one. although this is an 8-bit register the decimation is usually limited to between 1 and 32. decimations higher than 32 would require more scaling than the cic5 is capable of. 0x95: cic5 scale the cic5 scale factor is used to compensate for the growth of the cic5 filter. consult the cic5 section for details. 0x96: reserved (must be written low) 0xa0: rcf decimation ? 1 (m rcf -1) this register is used to set the decimation of the rcf stage. the value written is the decimation minus one. although this is an 8-bit register which allows decimation up to 256, for most filtering scenarios the decimation should be limited between 1 and 32. higher decimations are allowed but the alias protection of the rcf may not be acceptable for some applications. 0xa1: rcf decimation phase (p rcf ) this register allows any one of the m rcf phases of the filter to be used and can be adjusted dynamically. each time a filter is started then this phase is updated. when a channel is synchronized then it will retain the phase setting chosen here. this can be used as part of a timing recovery loop with an external processor or can allow multiple rcfs to work together while using a single rcf pair. the rcf section of the data sheet should be consulted for further details. 0xa2: rcf number of taps minus one (n rcf -1) the number of taps for the rcf filter minus one is written here. 0xa3: rcf coefficient offset (co rcf ) this register is used to specify which section of the 256- word coefficient memory is used for a filter. it can be used to select between multiple filters that are loaded into memory and referenced by this pointer. this register is shadowed and the filter pointer is updated every time a new filter is started. this allows the coefficient offset to be written even while a filter is being computed with disturbing operation. the next sample that comes out of the rcf will be with the new filter. 0xa4: rcf control register the rcf control register is an 11-bit register that controls general features of the rcf as well as output formatting. the bits of this register and their functions are described below. bit 10 bypasses the rcf filter and sends the cic5 output data to the bist-i and bist-q registers. the 16 msbs of the cic5 data can be accessed from this register if bit 9 of the rcf control register 2 at channel address 0xa9 is set. bit 9 of this register controls the source of the input data to the rcf. if this bit is 0 then the rcf processes the output data of it?s own channel. if this bit is 1 then it processes the data from the cic5 of another channel. the cic5 that the rcf is connected to when this bit is 1 are shown in the table xiv below. these can be used to allow multiple rcfs to be used together to process wider bandwidth channels. see the multi-processing section of the data- sheet for further details. channel rcf input source when bit-9 is 1 0 1 1 0 2 1 3 1 table xiv. rcf input configurations bit 8 is used as an extra address to allow a second block of 128 words of cmem to be addressed by the channel addresses at 0x00-0x7f. if this bit is 0 then the first 128 words are written and if this bit is 1 then a second 128 words is written. this bit is only used to program the coefficient memory. it is not used in any way by the processing and filters longer than 128 taps can be performed. bit 7 is used to help control the output formatting of the AD6652s rcf data. this bit is only used when the 8+4 or 12+4 floating-point modes are chosen. these modes are enable by bits 5 and 4 of this register below. when this bit is 0 then the i and q output exponents are determined separately based on their individual magnitudes. when this bit is 1 then the i and q data is a complex floating- point number where i and q use a single exponent that is determined based on the maximum magnitude of i or q. bit 6 is used to force the output scale factor in bits 3-0 of this register to be used to scale the data even when one of the floating point output modes is used. if the number
preliminary technical data AD6652 rev. pra 9/16/2002 55 was too large to represent with the output scale chosen then the mantissas of the i and q data clip and do not overflow. bits 5 and 4 choose the output formatting option used by the rcf data. the options are defined in the table xv below and are discussed further in the output format section of the data sheet. bit values output option 1x 12-bit mantissa and 4-bit exponent(12+4) 01 8-bit mantissa and 4-bit exponent(8+4) 00 fixed point mode table xv. output formats bits 3-0 of this register represent the output scale factor of the rcf. it is used to scale the data when the output format is in fixed-point mode or when the force exponent bit is high. 0xa5: bist register for i this register serves two purposes. the first is to allow the complete functionality of the i data path in the channel to be tested in the system. the bist section of the data sheet should be consulted for further details. the second function is to provide access to the i output data through the micro-port. to accomplish this the map rcf data to bist bit in the rcf control register 2, 0xa9, should be set high. 16-bits of i data can then be read through the micro port in either the 8+4, 12+4, 12 bit linear or 16-bit linear output modes. this data may come from either the formatted rcf output or the cic5 output. 0xa6: bist register for q this register serves two purposes. the first is to allow the complete functionality of q data path in the channel to be tested in the system. the bist section of the data sheet should be consulted for further details. the second function is to provide access to the q output data through the micro-port. to accomplish this the map rcf data to bist bit in the rcf control register 2, 0xa9, should be set high. 16-bits of q data can then be read through the micro port in either the 8+4, 12+4, 12 bit linear or 16-bit linear output modes. this data may come from either the formatted rcf output or the cic5 output. 0xa7: bist control register this register controls the number of outputs of the rcf or cic filter that are observed when a bist test is performed. the bist signature registers at addresses 0xa5 and 0xa6 will observe this number of outputs and then terminate. the loading of this register also starts the bist engine running. details of how to utilize the bist circuitry are defined in the bist section of the data sheet. 0xa8: ram bist control register this register is used to test the memories of the AD6652 should they ever be suspected of a failure. bit 0 of this register is written with a 1 when the channel is in sleep and the user waits for 1600 clks and then polls the bits. if bit 1 is high then the cmem failed the test and if bit 2 is high then the data memory used by the rcf failed the test. 0xa9: output control register bit 9 of this register allows the rcf or cic5 data to be mapped to the bist registers at addresses 0xa5 and 0xa6. when this bit is 0 then the bist register is in signature mode and ready for a self-test to be run. when this bit is 1 then the output data from the rcf after formatting or the cic5 data is mapped to these registers and can be read through the micro-port. bits 5 determines the word length used by the parallel port. if this bit is 0 then the parallel port uses 12 bit words for i and q. if this bit is 1 then the parallel port uses 16 bit words for i and q. when the fixed point output option is chosen from the rcf control register then these bits also set the rounding correctly in the output formatter of the rcf. remaining bits in this register are reserved and should be written low when programming. output port control registers in order to access the output port registers, bit 5 of the sleep register located in the external memory map must be written logic high. the car (channel address register) is then written with the address to the correct output port register. refer to table xvi below for a complete description of all registers. 0x00 through 0x07 these eight addresses are reserved and should be written logic low. 0x08 port a control register bit 0 enables the use of interpolating half band filter corresponding to port a. half band a can be used to interleave the data streams of multiple channels and interpolate by two providing a maximum output data rate of 4x the chip rate. it can be configured to listen to all four channels; channels 0, 1, 2, 3; channels 0, 1, 2; channels 0, 1; or only channel 0. half band a is bypassed when bit 0 = 1, in which case the outputs of the rcfs are directly sent to the agc. the channel data streams still get interleaved
preliminary technical data AD6652 rev. pra 9/16/2002 56 with the half band bypassed, but they are not filtered and interpolated. the maximum data rate from this configuration would be 2x the chip rate. 0x09 port b control register bit 0 enables the use of interpolating half band filter corresponding to port b. half band b can be used to interleave the data streams of multiple channels and interpolate by two providing a maximum output data rate of 4x the chip rate. it can be configured to listen to channels 2 and 3; or only channel 2. half band b is bypassed when bit 0 = 1, in which case the outputs of the rcfs are directly sent to the agc. the channel data streams still get interleaved with the half band bypassed, but they are not filtered and interpolated. the maximum data rate from this configuration would be 2x the chip rate. 0x0a agc a control register this 8-bit register controls features of the agc a. the bits are defined below: bits 7-5 define the output word length of the agc. the output word can be 4-8, 10, 12, or 16 bits wide. the control register bit representation to obtain different output word lengths is given in the memory map table. bit 4 of this register sets the mode of operation for the agc. when this bit is 0, the agc tracks to maintain the output signal level and when this bit is 1, the agc tracks to maintain a constant clipping error. consult the agc section for more details about these modes. the bits 3-1 are used to configure the synchronization of the agc. the cic decimator filter in the agc can be synchronized to an external sync signal to output an update sample for the agc error calculation and filtering. this way the agc gain changes can be synchronized to an external block like a rake receiver. whenever an external sync signal is received, the hold off counter at 0x0b is loaded and begins to count down. when the counter reaches one the cic filter dumps an update sample and starts working towards a new update sample. the agc can be initialized on each sync or only on the first sync. bit 3 is used to issue a command to the agc to sync immediately. if this bit is set the cic filter will update the agc with a new sample immediately and start operating towards the next update sample. the agc can be synchronized by the microport control interface using this method. bit 2 is used to determine whether the agc should initialize on a sync or not. when this bit is set, the cic filter is cleared and new values for cic decimation, number of averaging samples, cic scale, signal gain ?gs?, gain k and pole parameter ?p? are loaded. when bit2 = 0, the above-mentioned parameters are not updated and the cic filter is not cleared. in both cases an agc update sample is output from the cic filter and the decimator starts operating towards the next output sample whenever a sync occurs. bit 1 is used to ignore repetitive synchronization signals. in some applications, the synchronization signal may occur periodically. if this bit is clear, each synchronization request will re-synchronize the agc. if this bit is set only the first occurrence will cause the agc to synchronize and will update agc gain values periodically depending on the decimation factor of the agc cic filter. bit 0 is used to bypass the agc section, when it is set. the 23-bit representation from interpolating half band filters is still reduced to a lower bit width representation as set by bits 7-5 of the agc a control register. a truncation at the output of the agc accomplishes this task. 0x0b agc a hold off counter the agc a hold-off counter is loaded with the value written to this address when either a soft_sync or pin_sync comes into the channel. the counter begins counting down so when it reaches one, a sync is given to agc a. this sync may or may not initialize the agc, as defined by the control word. the agc loop is updated with a new sample from the cic filter whenever a sync occurs. if this register is written to one, the agc will be updated immediately when the sync occurs. if this register is written to a zero the agc cannot be synchronized. 0x0c agc a desired level this 8-bit register contains the desired output power level or desired clipping level depending on the mode of operation. this desired request ?r? level can be set in db from 0 to ?23.99 in steps of 0.094db. 8-bit binary floating- point representation is used with 2-bit exponent followed by 6 bit mantissa. mantissa is in steps of 0.094 db and exponent in 6.02 db steps. for example: 10?100101 represents 2 * 6.02 + 37 * 0.094 = 15.518db. 0x0d agc a signal gain this register is used to set the initial value for a signal gain used in the gain multiplier. this 12-bit value sets the initial signal gain between 0 and 96.296db in steps of 0.024db. 12-bit binary floating-point representation is used with 4-bit exponent followed by 8 bit mantissa. for example: 0111?10001001 is equivalent to 7 * 6.02 + 137 * 0.024 + 45.428db. 0x0e agc a loop gain
preliminary technical data AD6652 rev. pra 9/16/2002 57 this 8-bit register is used to define the open loop gain ?k?. its value can be set from 0 to 0.996 in steps of 0.0039. this value of ?k? is updated in the agc loop each time the agc is initialized. 0x0f agc a pole location this 8-bit register is used to define the open loop filter pole location ?p?. its value can be set from 0 to 0.996 in steps of 0.0039. this value of ?p? is updated in the agc loop each time the agc is initialized. this open loop pole location will directly impact the closed loop pole locations as explained in the agc section. 0x10 agc a average samples this 6-bit register contains the scale used for the cic filter and the number of power samples to be averaged before being fed to the cic filter. bits 5-2 define the scale used for the cic filter. bits 1-0 define the number of samples to be averaged before they are sent to the cic decimating filter. this number can be set between 1 and 4 with bit representation 00 meaning 1 sample and bit representation 11 meaning 4 samples. 0x11 agc a update decimation this 12-bit register sets the agc decimation ratio from 1 to 4096. an appropriate scaling factor should be set factor to avoid loss of bits. 0x12 agc b control register this 8-bit register controls features of the agc a. the bits are defined below: bits 7-5 define the output word length of the agc. the output word can be 4-8, 10, 12, or 16 bits wide. the control register bit representation to obtain different output word lengths is given in the memory map table. bit 4 of this register sets the mode of operation for the agc. when this bit is 0, the agc tracks to maintain the output signal level and when this bit is 1, the agc tracks to maintain a constant clipping error. consult the agc section for more details about these modes. the bits 3-1 are used to configure the synchronization of the agc. the cic decimator filter in the agc can be synchronized to an external sync signal to output an update sample for the agc error calculation and filtering. this way the agc gain changes can be synchronized to an external block like a rake receiver. whenever an external sync signal is received, the hold off counter at 0x0b is loaded and begins to count down. when the counter reaches one the cic filter dumps an update sample and starts working towards a new update sample. the agc can be initialized on each sync or only on the first sync. bit 3 is used to issue a command to the agc to sync immediately. if this bit is set the cic filter will update the agc with a new sample immediately and start operating towards the next update sample. the agc can be synchronized by the microport control interface using this method. bit 2 is used to determine whether the agc should initialize on a sync or not. when this bit is set, the cic filter is cleared and new values for cic decimation, number of averaging samples, cic scale, signal gain ?gs?, gain k and pole parameter ?p? are loaded. when bit2 = 0, the above-mentioned parameters are not updated and the cic filter is not cleared. in both cases an agc update sample is output from the cic filter and the decimator starts operating towards the next output sample whenever a sync occurs. bit 1 is used to ignore repetitive synchronization signals. in some applications, the synchronization signal may occur periodically. if this bit is clear, each synchronization request will re-synchronize the agc. if this bit is set only the first occurrence will cause the agc to synchronize and will update agc gain values periodically depending on the decimation factor of the agc cic filter. bit 0 is used to bypass the agc section, when it is set. the 23-bit representation from interpolating half band filters is still reduced to a lower bit width representation as set by bits 7-5 of the agc a control register. a truncation at the output of the agc accomplishes this task. 0x13 agc b hold off counter the agc a hold-off counter is loaded with the value written to this address when either a soft_sync or pin_sync comes into the channel. the counter begins counting down so when it reaches one, a sync is given to agc a. this sync may or may not initialize the agc, as defined by the control word. the agc loop is updated with a new sample from the cic filter whenever a sync occurs. if this register is written to one, the agc will be updated immediately when the sync occurs. if this register is written to a zero the agc cannot be synchronized. 0x14 agc b desired level
preliminary technical data AD6652 rev. pra 9/16/2002 58 this 8-bit register contains the desired output power level or desired clipping level depending on the mode of operation. this desired request ?r? level can be set in db from 0 to ?23.99 in steps of 0.094db. 8-bit binary floating- point representation is used with 2-bit exponent followed by 6 bit mantissa. mantissa is in steps of 0.094 db and exponent in 6.02 db steps. . for example: 10?100101 represents 2 * 6.02 + 37 * 0.094 = 15.518db 0x15 agc b signal gain this register is used to set the initial value for a signal gain used in the gain multiplier. this 12-bit value sets the initial signal gain between 0 and 96.296db in steps of 0.024db. 12-bit binary floating-point representation is used with 4-bit exponent followed by 8 bit mantissa. for example: 0111?10001001 is equivalent to 7 * 6.02 + 137 * 0.024 + 45.428db. 0x16 agc b loop gain this 8-bit register is used to define the open loop gain ?k?. its value can be set from 0 to 0.996 in steps of 0.0039. this value of ?k? is updated in the agc loop each time the agc is initialized. 0x17 agc b pole location this 8-bit register is used to define the open loop filter pole location ?p?. its value can be set from 0 to 0.996 in steps of 0.0039. this value of ?p? is updated in the agc loop each time the agc is initialized. this open loop pole location will directly impact the closed loop pole locations as explained in the agc section. 0x18 agc b average samples this 6-bit register contains the scale used for the cic filter and the number of power samples to be averaged before being fed to the cic filter. bits 5-2 define the scale used for the cic filter. bits 1-0 define the number of samples to be averaged before they are sent to the cic decimating filter. this number can be set between 1 and 4 with bit representation 00 meaning 1 sample and bit representation 11 meaning 4 samples. 0x19 agc b update decimation this 12-bit register sets the agc decimation ratio from 1 to 4096. an appropriate scaling factor should be set factor to avoid loss of bits. 0x1a parallel port control a data is output through either a parallel port interface or a link port interface. when 0x1b,bit 7 = 0, the use of link port a is disabled and the use of parallel port a is enabled. the parallel port provides different data modes for interfacing with dsps or fpgas. bit 0 selects which data is output on parallel port a. when bit 0 = 0, parallel port a outputs data from the rcf according to the format specified by bits 1 through 4. when bit 0 = 1, parallel port a outputs the data from the agcs according to the format specified by bits 1 and 2. in agc mode, bit 0 = 1 and bit 1 determines if parallel port a is able to output data from agc a and bit 2 determines if parallel port a is able to output data from agc b. the order of output depends on the rate of triggers from each agc, which in turn is determined by the decimation rate of the channels feeding it. in channel mode, bit 0 = 0 and bits 1 through 4 determine which combination of the four processing channels is output. the output order depends on the rate of triggers received from each channel, which is determined by the decimation rate of each channel. the channel output indicator pins can be used to determine which data came from which channel. bit 5 determines the format of the output data words. when bit 5 = 0, parallel port a outputs 16-bit words on its 16-bit bus. this means that i and q data are interleaved and the iq indicator pin determines whether data on the port is i data or q data. when bit 5 = 1, parallel port a is outputting an 8-bit i word and an 8-bit q word at the same time, and the iq indicator pins will be high. 0x1b link port control a data is output through either a parallel port interface or a link port interface. the link port provides an efficient data link between the AD6652 and a tigersharc dsp and can be enabled by setting 0x1d, bit 7 = 1. bit 0 selects which data is output on link port a. when bit 0 =0, link port a outputs data from the rcf according to the format specified by bit 1. when bit 0 = 1, link port a outputs the data from the agcs according to the format specified by bits 1 and 2. bit 1 has two different meanings that depend on whether data is coming from the agcs or from the rcfs. when data is coming from the rcfs (bit 0 = 0), bit 1 selects between two and four channel data mode. bit 1 = 1 indicates link port a transmits rcf iq words alternately from channels 0 and 1. when bit 1 = 1, link port a outputs rcf iq words from each of the four channels in succession: 0, 1, 2, then 3. however, when agc data is selected (bit 0 = 1), bit 1 selects the agc data output mode. in this mode, when bit 1 = 1, link port a outputs agc a iq and gain words. with this mode, gain words must be included by setting bit 2 = 0. however, if bit 0 = bit 1 = 0, then agc a and b are alternately output on link
preliminary technical data AD6652 rev. pra 9/16/2002 59 port a and the inclusion or exclusion of the gain words is determined by bit 2. bit 2 selects if gain words are included or not in the data output. if bit 1 = 1, bit 2 =0. since the gain words are only two bytes long and the iq words are four bytes long, the gain words are padded with zeros to give a full 16-byte tigersharc quad-word. if agc output is not selected (bit 0 = 0) then this bit can be any value. bits 6 through 3 specify the programmable delay value for link port a between the time the link port receives a data ready from the receiver and the time it transmits the first data word. the link port must wait at least 6 cycles of the receiver?s clock, so this value allows the user to use clocks of differing frequency and phase for the AD6652 link port and the tigersharc link port. there is more information on the limitations and relationship of these clocks in the section on link ports.
preliminary technical data AD6652 rev. pra 9/16/2002 60 table xvi: memory map for output port control registers address register bit width comments 00 01 02 03 04 05 06 07 10 10 20 6 10 10 20 5 reserved ? write all bits logic 0 reserved ? write all bits logic 0 reserved ? write all bits logic 0 reserved ? write all bits logic 0 reserved ? write all bits logic 0 reserved ? write all bits logic 0 reserved ? write all bits logic 0 reserved ? write all bits logic 0 08 port a control register 4 3: port a enable 2-1: hb a signal interleaveing 11 all 4 channels 10 chs 0, 1, 2 01 chs 0,1 00 ch 0 0: bypass 09 port b control register 3 2: port b enable 1: hb a signal interleaveing 1 chs 2, 3 0 ch 2 0: bypass 0a agc a control register 8 7-5: output word length 111 4 bits 110 5 bits 101 6 bits 100 7 bits 011 8 bits 010 10 bits 001 12 bits 000 16 bits 4: clipping error 1: maintain level of clipping error 0: maintain output signal level 3: sync now 2: init on sync 1: first sync only 0: bypass 0b agc a hold off counter 16 15-0: hold off value 0c agc a desired level 8 7-0: desired output power level or clipping energy (r parameter) 0d agc a signal gain 12 11-0: gs parameter 0e agc a loop gain 8 7-0: k parameter 0f agc a pole location 8 7-0: p parameter 10 agc a average samples 6 5-2: scale for cic decimator 1-0: number of averaging samples 11 agc a update decimation 12 11-0: cic decimation ratio 12 agc b control register 8 7-5: output word length 112 4 bits 110 5 bits 102 6 bits 101 7 bits 011 8 bits 010 10 bits 001 12 bits 000 16 bits 4: clipping error 1: maintain level of clipping error 0: maintain output signal level 3: sync now 2: init on sync 1: first sync only 0: bypass
preliminary technical data AD6652 rev. pra 9/16/2002 61 13 agc b hold off counter 16 15-0: hold off value 14 agc b desired level 8 7-0: desired output power level or clipping energy (r parameter) 15 agc b signal gain 12 11-0: gs parameter 16 agc b loop gain 8 7-0: k parameter 17 agc b pole location 8 7-0: p parameter 18 agc b average samples 6 5-2: scale for cic decimator 1-0: number of averaging samples 19 agc b update decimation 12 11-0: cic decimation 1a parallel a control 8 7-6: reserved 5: parallel port data format 1: 8-bit parallel i, q 0: 16-bit interleaved i, q 4: channel 3 3: channel 2 2: channel 1 / agc b enable 1: channel 0 / agc a enable 0: agc_ch select 1: data comes from agcs 0: data comes from channels 1b link a control 8 7: link port a enable 6-3: wait 2: no gain word 1: don?t output gain word 0: output gain word 1: channel data interleaved 1: 2 channel mode/separate ab 0: 4 channel mode/ab same port 0: agc_ch select 1: data comes from agcs 0: data comes from channels 1c parallel b control 8 7-6: reserved 5: parallel port data format 1: 8-bit parallel i, q 0: 16-bit interleaved i, q 4: channel 3 3: channel 2 2: channel 1 / agc b enable 1: channel 0 / agc a enable 0: agc_ch select 1: data comes from agcs 0: data comes from channels 1d link b control 8 7: link port b enable 6-3: wait 2: no gain word 1: don?t output gain word 0: output gain word 1: channel data interleaved 1: 2 channel mode/separate ab 0: 4 channel mode/ab same port 0: agc_ch select 1: data comes from agcs 0: data comes from channels 1e port clock control 3 2-1: pclk divisor 0: pclk master/slave 1 0: slave 1: master 1 pclk boots as slave.
preliminary technical data AD6652 rev. pra 9/16/2002 62 0x1c parallel port control b data is output through either a parallel port interface or a link port interface. when 0x1d, bit 7 = 0, the use of link port b is disabled and the use of parallel port b is enabled. the parallel port provides different data modes for interfacing with dsps or fpgas. bit 0 selects which data is output on parallel port b. when bit 0 = 0, parallel port b outputs data from the rcf according to the format specified by bits 1 through 4. when bit 0 = 1, parallel port b outputs the data from the agcs according to the format specified by bits 1 and 2. in agc mode, bit 0 = 1 and bit 1 determines if parallel port b is able to output data from agc a and bit 2 determines if parallel port b is able to output data from agc b. the order of output depends on the rate of triggers from each agc, which in turn is determined by the decimation rate of the channels feeding it. in channel mode, bit 0 = 0 and bits 1 through 4 determine which combination of the four processing channels is output. the output order depends on the rate of triggers received from each channel, which is determined by the decimation rate of each channel. the channel output indicator pins can be used to determine which data came from which channel. bit 5 determines the format of the output data words. when bit 5 = 0, parallel port b outputs 16-bit words on its 16-bit bus. this means that i and q data are interleaved and the iq indicator pin determines whether data on the port is i data or q data. when bit 5 = 1, parallel port b is outputting an 8-bit i word and an 8-bit q word at the same time, and the iq indicator pins will be high. 0x1d link port control b data is output through either a parallel port interface or a link port interface. the link port provides an efficient data link between the AD6652 and a tigersharc dsp and can be enabled by setting 0x1d, bit 7 = 1. bit 0 selects which data is output on link port b. when bit 0 =0, link port b outputs data from the rcf according to the format specified by bit 1. when bit 0 = 1, link port b outputs the data from the agcs according to the format specified by bits 1 and 2. bit 1 has two different meanings that depend on whether data is coming from the agcs or from the rcfs. when data is coming from the rcfs (bit 0 = 0), bit 1 selects between two and four channel data mode. bit 1 = 1 indicates link port a transmits rcf iq words alternately from channels 0 and 1. when bit 1 = 1, link port b outputs rcf iq words from each of the four channels in succession: 0, 1, 2, then 3. however, when agc data is selected (bit 0 = 1), bit 1 selects the agc data output mode. in this mode, when bit 1 = 1, link port b outputs agc b iq and gain words. with this mode, gain words must be included by setting bit 2 = 0. however, if bit 0 = bit 1 = 0, then agc a and b are alternately output on link port b and the inclusion or exclusion of the gain words is determined by bit 2. bit 2 selects if gain words are included or not in the data output. if bit 1 = 1, bit 2 =0. since the gain words are only two bytes long and the iq words are four bytes long, the gain words are padded with zeros to give a full 16-byte tigersharc quad-word. if agc output is not selected (bit 0 = 0) then this bit can be any value. bits 6 through 3 specify the programmable delay value for link port b between the time the link port receives a data ready from the receiver and the time it transmits the first data word. the link port must wait at least 6 cycles of the receiver?s clock, so this value allows the user to use clocks of differing frequency and phase for the AD6652 link port and the tigersharc link port. there is more information on the limitations and relationship of these clocks in the section on link ports. 0x1e port clock control bit 0 determines whether pclk is supplied externally by the user or derived internally in the AD6652. if pclk is derived internally from dclk (bit 0 = 1), it is output through the pclk pin as a master clock. for most applications, pclk will be provided by the user as an input to the AD6652 via the pclk pin. bits 2 and 1 allow the user to divide dclk by an integer value to generate pclk (00 = 1, 01 = 2, 10 = 4, 11 = 8). microport control the AD6652 has an 8-bit microprocessor port and a serial control port. the use of each of these ports is described separately below. the interaction of the ports is then described. the microport interface is a multi-mode interface that is designed to give flexibility when dealing with the host processor. there are two modes of bus operation: intel non-multiplexed mode (inm), and motorola non-multiplexed mode (mnm). the mode is selected based on host processor and which mode is best suited to that processor. the micro-port has an 8-bit data bus(d[7:0]), 3-bit address bus(a[2:0]), 3 control pins lines (/cs, /ds or /rd, rw or /wr), and one status pin(dtack or rdy). the functionality of the control signals and status line changes slightly depending upon the mode that is chosen. refer to the timing diagrams and the following descriptions for details on the operation of both modes.
preliminary technical data AD6652 rev. pra 9/16/2002 63 external memory map the external memory map is used to gain access to the channel address space described previously. the 8-bit data and address buses are used to this set of 8 registers that can be seen in the following table 16. these registers are collectively referred to as the external interface registers since they control all accesses to the channel address space as well as output control registers. the use of each of these individual registers is described below in detail. it should be noted that the serial control interface has the same memory map as the micro-port interface and can carry out the exact same functions, although at a slower rate. access control register (acr) the access control register serves to define the channel or channels that receive an access from the micro-port or serial port control. bit 7 of this register is the auto-increment bit. if this bit is a 1 then the car register described below will increment its value after every access to the channel. this allows blocks of address space such as coefficient memory to be initialized more efficiently. a[2:0] name comment 111 access control register (acr) 7: auto increment 6: broadcast 5-2: instruction[3:0] 1-0: a[9:8] 110 channel address registers (car) 7-0: a[7:0] 101 soft_sync control register (write only) 7: pn_en 6: test_mux_select 5: hop 4: start 3: sync d 2: sync c 1: sync b 0: sync a 100 pin_sync control register (write only) 7: reserved write to logic low 6: first sync only 5: hop_en 4: start_en 3: sync_en d 2: sync_en c 1: sync_en b 0: sync_en a 011 sleep (write only) 7-6: reserved write to logic low 5: access output port control registers 4: reserved low 3: sleep 3 2: sleep 2 1: sleep 1 0: sleep 0 010 data register 2 (dr2) 7-4: reserved 3-0: d[19:16] 001 data register 1 (dr1) 15-8: d[15:8] 000 data register 0 (dr0) 7-0: d[7:0] table xii. external memory map bit 6 of the register is the broadcast bit and determines how bits 5-2 are interpreted. if broadcast is 0 then bits 5-2, which are refereed to as instruction bits (instruction[3:0]), are compared with the chip_id[3:0] pins. the instruction which matches the chip_id[3:0] pins will determine the access. this allows up to 16 chips to be connected to the same port and memory mapped without external logic. this also allows the same serial port of a host processor to configure up to 16 chips. if the broadcast bit is high the instruction[3:0] word allows multiple AD6652 channels and/or chips to be configured simultaneously independent of the chip_id[3:0] pins. there are 10 possible instructions that are defined in table xiii below. instruction comment: 0000 all chips and all channels will get the access. 0001 channel 0,1,2 of all chips will get the access. 0010 channel 1,2,3 of all chips will get the access. 0100 all chips will get the access. 1 1000 all chips with chip_id[3:0] = xxx0 will get the access. 1 1001 all chips with chip_id[3:0] = xxx1 will get the access. 1 1100 all chips with chip_id[3:0] = xx00 will get the access. 1 1101 all chips with chip_id[3:0] = xx01 will get the access. 1 1110 all chips with chip_id[3:0] = xx10 will get the access. 1 1111 all chips with chip_id[3:0] = xx11 will get the access. 1 1 a[9:8] bits control which channel is decoded for access. table xiii. microport instructions
preliminary technical data AD6652 rev. pra 9/16/2002 64 this is useful for smart antenna systems where multiple channels listing to a single antenna or carrier can be configured simultaneously. the x?s in the comment portion of the table represent ?don?t cares? in the digital decoding. when broadcast is enabled (bit 6 set high) read back is not valid because of the potential for internal bus contention. therefore, if read back is subsequently desired, the broadcast bit should be set low. bits 1-0 of the acr are address bits that decode which of the four channels are being accessed. if the instruction bits decode an access to multiple channels then these bits are ignored. if the instruction decodes an access to a subset of chips then the a[9:8] bits will otherwise determine the channel being accessed. channel address register (car) this register represents the 8-bit internal address of each channel. if the auto-increment bit of the acr is 1 then this value will be incremented after every access to the dr0 register, which will in turn access the location pointed to by this address. the channel address register cannot be read back while the broadcast bit is set high. soft_sync control register external address [5] is the soft_sync control register and is write only. bit 0-3 of this register are the soft_sync control bits. these pins may be written to by the controller to initiate the synchronization of a selected channel. although there are 4 inputs, these do not necessarily go to the channel of the same number. this is fully configurable at the channel level as to which bit to look at. all 4 channels may be configured to synchronize from a single position, or they may be paired or all independent. bit 4 determines if the synchronization is to apply to a chip start. if this bit is set, a chip start will be initiated. bit 5 determines if the synchronization is to apply to a chip hop. if this bit is set, the nco frequency will be updated when the when the soft_sync occurs. bit 6 configures how the internal data bus is configured. if this bit is set low, then the internal adc data buses are configured normally. if this bit is set, then the internal test signals are selected. the internal test signals are configured in bit 7 of this register. bit 7 if set clear, a negative full scale signal is generated and made available to the internal data bus. if this bit is high, then internal pseudorandom sequence generator is enabled and this data is available to the internal data bus. the combined functions of bit 6 and 7 facilitate verification of a given filter design. also, in conjunction with the misr registers allows for detailed in-system chip testing. in conjunction with the jtag test board, very high levels of chip verification can be done during system test, both in the factory and field. pin_sync control register external address [4] is the pin_sync control register and is write only. bit 0-3 of this register are the sync_en control bits. these pins may be written to by the controller to allow pin synchronization of a selected sync channel. although there are 4 inputs, these do not necessarily go to the channel of the same number. this is fully configurable at the channel level as to which bit to look at. all 4 channels may be configured to synchronize from a single position, or they may be paired or all independent. bit 4 determines if the synchronization is to apply to a chip start. if this bit is set, a chip start will be initiated when the pin_sync occurs. bit 5 determines if the synchronization is to apply to a chip hop. if this bit is set, the nco frequency will be updated when the when the pin_sync occurs. bit 6 is used to ignore repetitive synchronization signals. in some applications, this signal may occur periodically. if this bit is clear, each pin_sync will restart/hop the channel. if this bit is set, then only the first occurrence will cause the chip to take action. bit 7 is used with bit 6 and 7 of external address 5. when this bit is cleared, the data supplied to the internal data bus simulates a normal adc. when this bit is set, the data supplied is in the form of a time multiplexed adc such as the ad6600 (this allows the equivalent of testing in the 4 channel input mode). internally, when set, this bit forces the ien pin to toggle as if it were driven by the a/b signal of the ad6600. sleep control register external address [3] is the sleep register. bits 3-0 control the state of each of the channels. each bit corresponds to one of the possible rsp channels within the device. if this bit is cleared, the channel operates normally. however, when this bit is set, the indicated channel enters a low power sleep mode. bit 4 is reserved and should be set to 0 always.
preliminary technical data AD6652 rev. pra 9/16/2002 65 bit 5 allows access to the output control port registers at channel addresses 00-1e. when this bit is set low, the channel memory map is accessed. however, when this bit is set high, it allows access to the output port control registers. when this bit is set high, the value in external address 6 (car) points to the memory map for the output port control registers instead of the normal channel memory map. see output port control registers in the output memory map section. bit 6-7 are reserved and should be written low. data address registers external address [2-0] form the data registers dr2, dr1 and dr0 respectively. all internal data words have widths that are less than or equal to 20 bits. accesses to external address [0] dr0 trigger an internal access to the AD6652 based on the address indicated in the acr and car. thus during writes to the internal registers, external address [0] dr0 must be written last. at this point data is transferred to the internal memory indicated in a[9:0]. reads are performed in the opposite direction. once the address is set, external address [0] dr0must be the first data register read to initiate an internal access. dr2 is only 4 bits wide. data written to the upper 4 bits of this register will be ignored. likewise reading from this register will produce only 4 lsbs. write sequencing writing to an internal location is achieved by first writing the upper two bits of the address to bits 1 through 0 of the acr. bits 7:2 may be set to select the channel as indicated above. the car is then written with the lower eight bits of the internal address (it doesn?t matter if the car is written before the acr as long as both are written before the internal access). data register 2,(dr2) and register 1 (dr1) must be written first because the write to data register dr0 triggers the internal access. data register dr0 must always be the last register written to initiate the internal write. read sequencing reading from the micro port is accomplished in the same manner. the internal address is set up the same way as the write. a read from data register dr0 activates the internal read, thus register dr0 must always be read first to initiate an internal read followed by dr1and dr2. this provides the 8 lsbs of the internal read through the micro port (d[7:0]). additional data registers can be read to read the balance of the internal memory. read/write chaining the micro port of the AD6652 allows for multiple accesses while /cs is held low (/cs can be tied permanently low if the micro port is not shared with additional devices). the user can access multiple locations by pulsing the /wr or /rd line and changing the contents of the external three bit address bus. external access to the external registers of table 13 is accomplished in one of two modes using the /cs, /rd, /wr, and mode inputs. the access modes are intel non-multiplexed mode and motorola non- multiplexed mode. these modes are controlled by the mode input (mode=0 for inm, mode=1 for mnm). /cs, /rd, and /wr control the access type for each mode. intel non-multiplexed mode (inm) mode must be tied low to operate the AD6652 microprocessor in inm mode. the access type is controlled by the user with the /cs, /rd (/ds), and /wr (rw) inputs. the rdy (/dtack) signal is produced by the micro port to communicate to the user that an access has been completed. rdy (/dtack) goes low at the start of the access and is released when the internal cycle is complete. see the timing diagrams for both the read and write modes in the specifications. motorola non-multiplexed mode (mnm) mode must be tied high to operate the AD6652 microprocessor in mnm mode. the access type is controlled by the user with the /cs, /ds (/rd), and rw (/wr) inputs. the /dtack (rdy) signal is produced by the micro port to communicate to the user that an access has been completed. /dtack (rdy) goes low when an internal access is complete and then will return high after /ds (/rd) is de-asserted. see the timing diagrams for both the read and write modes in the specifications. serial port control the AD6652 has a serial port serving as a control interface apart from the microport control interface. serial port input pin (sdin) can access all of the internal registers for all of the channels and has preemptive access over the microport. in this manner, a single dsp could be used to control the AD6652 over the serial port control interface. the serial control port uses the serial clock (sclk). the serial input port is self-framing as described below and allows more efficient use of the serial input bandwidth for programming. the beginning of a serial input frame is signaled by a frame bit that appears on the sdin pin. this is the msb of the serial input frame. after the frame bit has been sampled high on the falling edge of sclk a state counter will start and enable an 11 bit serial shifter 4 serial clock cycles later. these 4 sclk cycles represent the ?don?t care? bits of the serial frame that are
preliminary technical data AD6652 rev. pra 9/16/2002 66 ignored. after all of the bits are shifted then the serial input port will pass along the 8-bit data and 3-bit address to the arbitration block. the serial word structure for the sdin input is illustrated in the figure 48 below. only 15 bits are listed so that the second bit in a standard 16-bit serial word is considered the frame bit. this is done for compatibility with the ad6620 serial input port. the shifting order begins with frame and shifts the address msb first and then the data msb first. serial port timing specifications the AD6652 serial control channel can operate only in the slave mode. the diagrams below indicate the required timing for each of the specification. t sclk t sclkl t sclkh sclk figure 43. sclk timing requirements sclk clk t dsclkh t sclkl t sclkh figure 44. sclk switching characteristics (divide by 1 ) t ssi t hsi sclk sdin data figure 45. serial input data timing requirements sdin sdin is the serial data input. serial data is sampled on the falling edge of sclk. this pin is used in the serial control mode to write the internal control registers of the AD6652. sclk sclk is a clock input and the sdin input is sampled on the falling edge of sclk and all outputs are switched on the rising edge of sclk. the maximum speed of this port is 65mhz. frame x x x x a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sdi sclk t ssi clkn frame x figure 46. serial word structure and serial port control timing
preliminary technical data AD6652 rev. pra 9/16/2002 67 jtag boundary scan the AD6652 supports a subset of ieee standard 1149.1 specification. for additional details of the standard, please see ?ieee standard test access port and boundary-scan architecture,? ieee-1149 publication from ieee. the AD6652 has five pins associated with the jtag interface. these pins are used to access the on-chip test access port and are listed in the table below. all input jtag pins are pull up except for tclk which is a pull down. name pin number description /trst 67 test access port reset tclk 68 test clock tms 69 test access port mode select tdi 72 test data input tdo 70 test data output table xx. boundary scan test pins the AD6652 supports six op codes as shown below. these instructions set the mode of the jtag interface. instruction op code idcode 001 bypass 111 sample/preload 010 extest 000 highz 011 clamp 100 table xxi. boundary scan op codes the vendor identification code can be accessed through the idcode instruction and has the following format. msb version part number manufacturin g id # lsb mandator y 0000 0010 0111 1000 1100 000 1110 0101 1 table xxii. vendor id code a bsdl file for this device is available, please contact analog devices inc. for more information. extest (3'b000) -> places the ic into an external boundary-test mode and selects the boundary-scan register to be connected between tdi and tdo. during this, the boundary-scan register is accessed to drive test data off- chip via boundary outputs and receive test data off-chip from boundary inputs. idcode (3'b001) -> allows the ic to remain in its functional mode and selects device id register to be connected between tdi and tdo. accessing the id register does not interfere with the operation of the ic. sample/preload (3'b010) -> allows the ic to remain in normal functional mode and selects the boundary-scan register to be connected between tdi and tdo. the boundary-scan register can be accessed by a scan operation to take a sample of the functional data entering and leaving the ic. also, test data can be preloaded into the boundary scan register before an extest instruction. highz (3'b011) -> sets all outputs to high impedance state. selects one-bit bypass register to be connected between tdi and tdo. clamp (3'b100) -> sets the outputs of the ic to logic levels determined by the boundary-scan register and selects one-bit bypass register to be connected between tdi and tdo. before this instruction, boundary-scan data can be preloaded with the sample/preload instruction. bypass (3'b111) -> allows the ic to remain in normal functional mode and selects one-bit bypass register between tdi and tdo. during this instruction, serial data is transferred from tdi to tdo without affecting operation of the ic. internal write access up to 20-bits of data (as needed) can be written by the process described below. any high order bytes that are needed are written to the corresponding data registers defined in the external 3-bit address space. the least significant byte is then written to dr0 at address (000). when a write to dr0 is detected, the internal microprocessor port state machine then moves the data in dr2-dr0 to the internal address pointed to by the address in the lar and amr. write pseudocode void write_micro(ext_address, int data); main(); { /* this code shows the programming of the nco phase offset register using the write_micro function as defined above. the variable address is the external address
preliminary technical data AD6652 rev. pra 9/16/2002 68 a[2:0] and data is the value to be placed in the external interface register. internal address = 0x087 */ // holding registers for nco phase byte wide access data int d1, d0; // nco frequency word (16-bits wide) nco_phase = 0xcbef; // write acr write_micro(7, 0x03 ); // write car write_micro(6, 0x87); // write dr1 with d[15:8] d1 = (nco_phase & 0xff00) >> 8; write_micro(1, d1); // write dr0 with d[7:0] // on this write all data is transferred to the internal address d0 = nco_freq & 0xff; write_micro(0, d0); } // end of main internal read access a read is performed by first writing the car and amr as with a write. the data registers (dr2-dr0) are then read in the reverse order that they were written. first, the least significant byte of the data (d[7:0]) is read from dr0. on this transaction the high bytes of the data are moved from the internal address pointed to by the car and amr into the remaining data registers (dr2-dr1). this data can then be read from the data registers using the appropriate 3 bit addresses. the number of data registers used depends solely on the amount of data to be read or written. any unused bit in a data register should be masked out for a read. read pseudocode int read_micro(ext_address); main(); { /* this code shows the reading of the first rcf coefficient using the read_micro function as defined above. the variable address is the external address a[2..0]. internal address = 0x000 */ // holding registers for the coefficient int d2, d1, d0; // coefficient (20-bits wide) long coefficient; // write amr write_micro(7, 0x00 ); // write lar write_micro(6, 0x00); /* read d[7:0] from dr0, all data is moved from the internal registers to the interface registers on this access */ d0 = read_micro(0) & 0xff; // read d[15:8] from dr1 d1 = read_micro(1) & 0xff; // read d[23:16] from dr2 d2 = read_micro(2) & 0x0f; coefficient = d0 + (d1 << 8) + (d2 << 16); } // end of main AD6652 evaluation board and software a fully populated AD6652 evaluation board kit, operating software and digital filter design software are available. the evaluation pcb kit is provided with a comprehensive instruction manual.

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